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60 The PCB Design Magazine • March 2015 the trace. This also provides the smallest loop area. When a trace crosses a gap in the adjacent plane, the return current is diverted from un- derneath the trace in order to go around the gap. This causes the current to flow through a much larger loop area which changes the char- acteristic impedance of the trace, increases the crosstalk between adjacent traces, and thus in- creases the radiation from the board. In some instances, the return current may have to go all the way back to the power supply. A major EMC problem occurs when there are discontinuities in the current return path. Routing traces via the pass-through gap alleviates these problems and still allows vital signals to enter and leave the sensitive area. The return current will al- ways follow the signal traces and will not go through other areas. Also, there is the issue of what to do with all the different power supplies for the major chips without splitting the planes. These days, it is typical to have six or more different sup- plies. In fact, a DDR3 motherboard that I just completed had a count of 30 different supplies plus an analog and a digital ground. On a com- plex multilayer board, it is typical to use eight or more layers, four of these being planes. Figure 2 shows how the ICD Stackup Plan- ner was used to calculate the impedance of the traces and to plan the stackup of the PCB sub- strate using multiple supplies. This may at first look unusual for DDR3 design, but the addi- tion of copper pours on the dual stripline layers changes everything. Power planes are on layers 5 and 6 and are also placed as pours under the chips on the top and bottom layers. However, pouring copper over the entire outer layers is not recommended. With this particular design, ground pours were added to layers 4 and 7 un- der the DDR3 devices, to drop the impedance in these areas to 40/80 ohm single-ended/dif- ferential. Figure 3 shows layer 4 as GND and the impedance has been altered to 40/80 ohms with the addition of this plane under the DDR3 devices. This also provides good planar capaci- tance and stability for the 1.5V power distribu- tion network (PDN). beyond design Figure 2: A 10-layer DDR3 stackup. SPLIT PLAnES In MULTILAyER PCBS continues

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