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60 The PCB Design Magazine • April 2015 Recalling the earlier experiment, increasing the dielectric constant negatively affected the available capacitance by shrinking the effective radius, and thus the area. This still very much holds true, but if the plane area is smaller than the effective area, then it isn't being fully uti- lized by the current sink. In this case, decreas- ing the effective area by increasing the dielectric constant will increase the available capacitance and should lower the noise voltage. One has to calculate how much the dielec- tric constant can be increased, as to fully utilize the available plane area, but not so much as to shrink the effective area below the PCB plane area. In our case, the plane area is 2 in 2 , which gives a capacitance of 645pF when the dielectric constant is 4.3 and the spacing is 3 mils. Since the area is 2 in 2 , the radius (r) must equal 0.797 in. Solving Equation 2 for the dielectric constant using this radius yields ~ 14, which tells us we can increase the dielectric constant all the way up to 14, shrinking the effective area to match the current sink. By doing this we can fully uti- lize the plane area in a way that maximizes the capacitance and lowers the noise voltage. Calculating the capacitance for both cases yields 645pF for the standard dielectric con- stant of 4.3 and 2.12nF for the high dielectric case. Running the simulation with the dielec- tric constant = 14 for all power plane layers is shown in Figure 9. Right away we notice that the noise voltage at the current sink hasn't changed much (delta of ~12mV), but the noise voltage at the plane edges has decreased by 66mV. In this case local decoupling of the cur- rent sink should also help suppress the noise voltage. As a final thought, we could decrease the spacing and add additional plane pairs to in- crease the capacitance of the PCB. Simply chang- ing the plane pair spacing to be 1 mil yields a noise voltage of only 22mV at the edges and 33.5mV at the current sink. Adding in an ad- ditional layer and leaving the spacing at 3 mils yields a noise voltage of 39.3mV at the current sink and 23mV at the edges of the PCB. The best scenario for this experiment is to change the power plane spacing to 1 mil as well as add an additional layer when using the high dielectric material. In this case the noise voltage simulates as only 15.5mV at the current sink and 8.5mV at the PCB edges. Conclusions Designing a stack-up and PDN can be a difficult task as there are many factors to con- sider for proper performance. Often times me- chanical, thermal, and cost constraints impact the number of layers, the materials, and the amount of time that can be spent analyzing the design. It is also important to note that real designs have many complex current sinks, with many different dynamic characteristics. A traditional method of estimating these cur - rents is to simulate the I/O of a device(s) and look at the driver I/O current spectrum to bet- ter understand the switching activity of these devices 1 . From this frequency spectrum, one can gain a better understanding of the load dynamics, and how to gauge the effective ra- dius. With all simulations, it isn't an exact sci- ence. Sometimes, the most important thing you can find out is what scenarios yield the greatest impact given the amount of informa- tion available. article Figure 8: Results of experiment 6. The total board area is considerably smaller than the effective area. The peak noise voltage is 129.4mv located at the edges whereas the voltage at the current sink is approximately 106mv. EFFECTIvE DECoUPLING RADIUS continues

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