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PCBD-Apr2015

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April 2015 • The PCB Design Magazine 59 article layer 6. The dielectric constant is set back to 4.3 and the spacing is set to 3 mils between plane pairs. Figure 7 shows the results of the simulation having a peak noise voltage of only 39.1mV at the current sink. What happens if we shrink the spacing between the power planes to 1 mil? From our previous experiments we can take an educated guess that the capacitance should increase and it should improve our noise voltage. Running this scenario concludes this and shows a peak noise voltage of only 15.4mV! You may ask when a scenario like this is appropriate. Consider a memory system such as DDR2. Often the manufacturer will specify that byte lanes be routed on different layers for crosstalk, timing, trace impedance, and other constraints. In a system like this you will likely be forced to use multiple split planes for your PDN to accommodate other devices as well. In a system like DDR2, it makes sense for all of your signals to use either GND or a 1.8V power plane as a reference (return) plane since this is the nominal power loop where the cur - rent is drawn from. Using a reference plane that is not in the nominal current loop (say 3.3V) may not be a good choice. In this situa- tion, the plane that is 3.3V could be split and connected to 1.8V in the area where the DDR2 nets are routed. This way the signals are refer- encing a power plane (or GND) that is in the nominal power loop and providing additional capacitance for the switching currents. One still needs to calculate the effective radius of the memory system by simulating/calculating the edge rates of the system. From here, the designer can grasp an idea of how large the plane area needs to be. Obviously, the place - ment/routing area of the memory system need to be considered as well when deciding where to place splits. Always extend the plane so that signals aren't routed over splits whenever pos- sible, even if the plane area is larger than the calculated effective area dictates. Experiment 6: Board Area is Smaller than the Effective Area Our previous experiments only looked at the board when it was either similar or much larger than the effective area of the current sink. So what if the area of the PCB is smaller, or much smaller than the calculated effective area? What are the best solutions in this case? For this experiment, we will use the same current sink properties yielding an effective ra- dius of 1.45 in and an area of 6.60 in 2 . However, the board area will be considerably smaller—2 in 2 (1.41 x 1.41 in). The stack-up has been set back to 3 mil spacing, dielectric constant of 4.3, with the current sink and VRM connected to just layer 2 as previously. Figure 8 shows the results of the simulation. Here we see the peak noise voltage is worse at the edges of the board (129.4mV) versus at the current sink (106mV). The board geometry is also playing a role as there are modal resonances occurring different- ly than with the larger board. We can conclude that both decreasing the dielectric spacing between the layers and using additional planes will decrease our noise volt- age by increasing the capacitance of the system. What about increasing the dielectric constant to something higher? Figure 7: showing the results of experiment 5. layer 6 is now connected to layer 2 by stitching vias to increase the effective capacitance con- nected to the current sink. Both layers 2 and 6 are sized so that they are similar to the calculated effective area. The peak noise voltage is only 39.1mv. EFFECTIvE DECoUPLING RADIUS continues

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