SMT007 Magazine

SMT-May2015

Issue link: https://iconnect007.uberflip.com/i/505968

Contents of this Issue

Navigation

Page 13 of 74

14 SMT Magazine • May 2015 pendent. Many of today's products leave little room for designing the mechanics in the most reliable way due to total cost and overall look and size of the products. This article will discuss different layouts, assembly and material selections to reduce component-to-component spacing down to 100–125 µm (4–5 mil) from today's mainstream of 150–200 µm (6–8 mil) component-to-com- ponent spacing. Introduction With the neverending drive for smaller, lighter and more advanced features on portable products, the ability to handle miniaturization is becoming a key capability to enable these requirements. Miniaturization can be done in many ways and this article touches on the as- sembly technologies that can be incorporated in a more or less standard surface mount assem- bly line with minimal equipment and material upgrades. Before starting any development work it is critical to understand product and industry re- quirements and capabilities. If this is not fully understood, no development activities can start. PCB fabrication can be seen as a good example on the importance of understanding require- ments and capabilities. If a good quality PCB can't be sourced within the scope of the assem- bly development project there is no reason to develop an assembly technology process since there is not anything to do the assembly devel- opment work on. The key is to ensure that sev- eral options for assembly can be achieved and this should be seen as a toolbox of technologies. For the active components die stacking in- side a package is one common way to increase the functionality per unit area on a PCBA, which is very popular for memory devices. Howev- er, there can be some drawbacks to creating a stacked die solution. First, this method is a cus- tomized solution. If any of the dies to be used changes, the die stack needs to be evaluated to see if changes are needed in the package. For example, a die shrink may occur and this could change the whole package structure. Secondly, if one or more of the dies inside the package fail, the whole unit will have to be scrapped, which would lead to increased cost; this is the well-known compounded yield issue. Lastly, trying to coordinate the many semiconductor suppliers to provide dies to a packaging house for die stacking can be a challenging task and overall responsibility for the complete package yield could in some cases be unclear. In the PoP process one component is placed on top of another package during a single SMT process to fully utilize the three dimensional as- pect of the product. The topside of the bottom component has pads similar to the pads on the PCB for attachment of the top package. Each package is a single unit that can be fully tested as a normal IC package is done today, so the yield would be comparable to the normal yield com- monly seen today. Another advantage would be the ability to have second-source options that could be fairly easily inserted into the process. The stacked package can be processed in a tra- ditional SMT environment with a few upgrades that are readily available. Therefore, package stacking enables configurable assemblies and provides greater flexibility in the supply chain. It can be used for memory applications or for a processor with memory, with faster time to market and better management of package test- ing and compounded yield issues. Reduced pitch is without doubt one of the bigger challenges for the active components, but it is a very effective way to achieve miniatur- ization. Today mainstream is 0.4 mm pitch, but 0.3 mm pitch is getting more and more popular. Taking the step to 0.3 mm from 0.4 mm poses a number of challenges mainly related to PCB design, screen printing and getting good qual- ity PCBs. For 0.3 mm pitch, our studies show that screen printing is a big challenge and a dip fluxing process might be needed for some ap- plications. This might sound like a big change, but the process for running an in-line flip chip or package-on-package process is more or less in place since many production lines are already using this process. With regards to passive components, two very effective ways to achieve miniaturization include using smaller parts such as 0201 and 01005 and reducing component-to-component spacing. Both strategies are very much feasible, but each needs to be carefully considered with the help of analyzing process data and total cost. mINIaTURIzaTION WITH THE HELP OF REDUCED COmPONENT-TO-COmPONENT SPaCING continues Feature

Articles in this issue

Archives of this issue

view archives of SMT007 Magazine - SMT-May2015