SMT007 Magazine

SMT-June2015

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14 SMT Magazine • June 2015 a premium. The current test strategy for these HDI PCBA types utilizes AOI, AXI and ICT to pre-screen manufacturing defects like shorts, opens, and wrong/bad component, so that FT can use precious test time to verify the func- tionality of the PCBA. Reduced test coverage of manufacturing defects makes it more challeng- ing to diagnose the correct defect. FT does not pinpoint the defect. What it does do is present the symptoms so that the debug technician can manually diagnose the failure mechanism and find the defect. Testing HDI PCBA Designs There is a need to innovate the manufactur- ing test strategy for HDI PCBA designs. Vision inspection technologies will be severely chal- lenged and defect call accuracy will decrease, with fine pitch array packages increasing the proportion of non-visible solder joints with less solder volume. A complementary limited ac- cess electrical test technology is needed to fill the test coverage void of AOI, AXI and ICT. IEEE 1687 is one possible solution, but it will be a few years before an IEEE 1687-compliant IC is com- mercially available. It took almost 10 years for IEEE 1149.1 to gain critical mass. IC designers had to start incorporating boundary scan cells in the silicon and allocating 4 I/O (TRST is op- tional) in the IC package before PCBA designers could even design-in the use of boundary scan ICs and begin chaining them from the TDO of an IC to the TDI of the next IC. Hopefully the pace of silicon implementation and adoption will be faster for IEEE 1687. The concept of IEEE 1687 is to use the IEEE 1149.1 pins (i.e., TMS, TDI, TDO, TCK and op- tional TRST) to put the IC into a test mode to control and exercise on-chip functionality and if possible, using the IC's outputs, to interact with surrounding devices. Both IEEE 1149.1 and IEEE 1687 are standards designed to guide IC designers to create in-chip access, indepen- dent of the core logic, for the sole purpose of IC verification when it is attached on a PCBA. Embedded Board Test (EBT) uses the IEEE defined in-chip access to verify that the IC is attached to the PCBA and in good working con- dition. It then extends the tests to surrounding components and potentially drives through to test ICs further away. Silicon nails and cover- extend are examples of extending tests through an IEEE 1149.1-compliant device to DDRs and connectors, respectively. HIGH-DenSITy InTeRCOnneCT AnD eMBeDDeD BOARD TeST continues Feature figure 5: The concept of embedded board test uses the ieee 1149.1 boundary scan and silicon view technology.

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