SMT007 Magazine

SMT-June2015

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June 2015 • SMT Magazine 15 IEEE 1687 is in its infancy with no compli- ant device available. Intel ® Silicon View Tech- nology (SVT), though not IEEE 1687 compliant, embodies the embedded board test concept. SVT works in tandem with the BIOS as the PCBA boots to discover internal devices and initialize communications, and interacts with surround- ing ICs. It can be used to extend tests to the edge of the PCBA, gaining test coverage for con- nectors to display and USB ports. Intel SVT is available today for the code-named microarchi- tectures Haswell, Broadwell and the upcoming Skylake. HDI designs for tablets and notebooks with limited test access will benefit from the ad- ditional test coverage gained by Intel SVT. Fig- ure 5 illustrates the combined test coverage of the EBT concept. The EBT testing concept suits HDI PCBA de- signs in which one or more CPU or SoC func- tions as the 'brain.' The test coverage for such HDI PCBA designs will be high since the CPU or SoC can exercise almost all internal functions and extend it through to the PCBA edge. Successful adoption of EBT requires it to be crafted early in PCBA design to develop the test software as the PCBA design evolves and ma- tures. Ideally, EBT should be deployed starting from the first PCBA prototype build and con- tinuing on to mass production; evolving the EBT test program to increment the test coverage progressively and maturing it prior to manufac- turing release. The initial investment to adopt any new technology is high, but the cost amor- tizes across subsequent PCBA designs and mod- els; increasing the electrical test coverage to sus- tain and potentially improve FT yields to return the investment. Test coverage lost due to buried traces can be recovered using EBT, which makes it a comple- mentary test to ICT. Pairing ICT and EBT is ideal as ICT can perform unpowered tests to locate and pinpoint short and open defects, as well as wrong components. This ensures the PCBA can safely power up for EBT to continue testing through the CPU or SoC to the PCBA edge. Fig- ure 6 illustrates the impact of EBT to the post- reflow test of the HDI PCBA. A key ingredient in the success of EBT, simi- lar to ICT and FT, is the test fixture and fixture automation. Design for Test (DFT) is critical for electrical test to design-in and layout test pads to realize the complementary test coverage of ICT, EBT and FT. Repeatability and reliability of the test fixture to accurately make the probes contact the test pads will reduce false fails so the tester can deliver its full value. Automating the insertion and sequencing of connectors to the PCBA edge for loopback connectivity test will eliminate human mistakes and achieve consistent test cycle times. The demand for me- chanical precision and probe targeting accuracy increases as test pad and connector sizes shrink. The electrical testing of the HDI PCBA requires the tester, test fixture and fixture automation to work as a single solution to maximize its poten- tial. It also requires one owner to architect, plan and implement the test solution; not three indi- vidual test vendors just contributing their parts. HDI PCBA for a server has sufficient PCB real estate to accommodate test access to more than 80 percent of total nets. The test strat- egy will continue to use ICT at the first stage of electrical test with empty CPU socket(s) and empty DIMM slots. EBT offers an alternative to exercising the PCBA with the inserted CPU(s) and DIMMs in a bench-top station setup after ICT. The CPU(s) and DDRs are usually soldered down for microservers so the test strategy of a HIGH-DenSITy InTeRCOnneCT AnD eMBeDDeD BOARD TeST continues Feature Figure 6: eBT complements icT and positively impacts the post-reflow test for hDi PcBA.

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