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18 SMT Magazine • June 2015 Introduction: Boosting ICT to Improve Testability Popular ICT platforms from well-known vendors can perform a wide variety of analogue, digital, powered, and unpowered tests to verify the integrity of electronic assemblies. In addi- tion to basic opens and shorts testing, analogue test capabilities include resistor, capacitor, po- tentiometer, diode and transistor tests. They can also verify power rails, and can generate digital test vectors as well as analogue waveforms to check for circuit functionality. The test coverage that can be achieved using a bed of nails fixture alone is becoming increas- ingly limited. The biggest problem here is that any component pins not extending through to the probed side of the assembly are not acces- by Robert Thompson XJTAG test Match—Partnering specialist Boundary-scan with ICt sible to the fixture nails unless the individual nets connected to it are exposed via unmasked vias, attached thru-hole connectors, or test points. The process of adding test access for ICT increases the cost of design, layout, and manu- facturing: extra vias, extra test points, and extra routing necessities all increase the overall com- plexity of the assembly. Physical test access is not free. Boundary-scan, used in conjunction with fixture-based tests, can extend test coverage on boards where test access is limited, and is critical to providing powered-shorts, opens and core- logic testing. IEEE 1149.1 compliant boundary- scan devices have the capability of driving and measuring pin states without physical access to the pin using a tester probe. ICT vendors inte- grate boundary-scan capabilities developed in- house to provide basic scan functionality that is native to the test platform, but this is not with- out its drawbacks. Feature