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50 The PCB Design Magazine • September 2015 Meanwhile back in Australia, where I was responsible for Intergraph Electronics sales and support, customers were also suitably im- pressed. My first sale was six seats of VeriBest PCB with 20 seats of Design Capture to Fujitsu Australia, who had previously used Cadence. Both Cadence and Mentor presented their flag- ship products (Allegro and Board Station, re- spectively), but the VeriBest router was so im- pressive that the competition did not rate men- tioning. Ron Oates, CAD manager of Fujitsu Australia at that time, stated in a press release, "VeriBest is light years ahead of the competi- tors." And it is still arguably the best routing technology available today. Mentor went on to acquire VeriBest in 1999, as the lack of routing technology formed a fairly large hole in their PCB offerings. Needless to say, Mentor's stock rose 9% after the acquisition was announced. I won't bore you with a full list of function- ality or standard EDA tool features, but rather I will take you through, in detail, what I see as the outstanding features of PADS Professional. PADS Professional utilizes xDX Designer as the front-end design entry tool. This schematic capture package was originally a ViewLogic Sys- tems tools called ViewDraw, which became the unified front-end tool for all Mentor PCB prod- ucts some years ago following an acquisition. Originally developed for creating hardware de- scription language (HDL) function blocks for digital and mixed-signal systems, such as FP- GAs and ASICs, it has a multitude of interfaces and is adaptable to many environments. In the PADS environment, it interfaces to the PCB (of course) but also allows FPGA I/O optimization, the integration of library tools, DxDatabook, and downstream digital and analog (EZWave) simulation tools. But as far as I am concerned, the ability to launch HyperLynx LineSim at the schematic level is its best attribute. After selecting a net, the LineSim link loads the data from xDX De- signer and exports it to HyperLynx to create a pre-layout free-form schematic view of the nets topology as in Figure 2. You can then simulate a beyond design Figure 2: DDR3 memory address net topology exported to LineSim. ToP GEAR: PADS PRoFESSIoNAl RoAD TEST