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PCB-Dec2015

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106 The PCB Magazine • December 2015 cency. This means that it is limited to the sur- face of the same layer. A single net is tested to all adjacent nets within the predetermined win- dow. Industry standard for this window is .050" (1.27 mm.) The primary net is tested to all nets within that window. Nets outside that window to the primary net are disregarded. The other type of adjacency is Z-axis, or ver- tical adjacency. In this method, not only are the line-of-sight nets checked to the adjacency win- dow but also nets on the adjacent layers within the predefined Z-axis window. More fabrication information is required for programming Z-axis adjacency. The stack-up of the PCB must be cal- culated. Specific thicknesses of dielectrics and core materials are used to define the appropriate adjacency window. If not calculated correctly the window may be created too large and acci- dentally pick up a layer too far away and cause excess test time, or be calculated too small and not test as required. Another hybrid feature in adjacency testing is the ability to create multiple adjacency win- dows on the same layer. This can be helpful if the PCB has a mix of tight trace/space coupled with other areas with larger spacing than the stan- dard .050" window. One can define the .050" window for the areas of the product where the finer pitch/spacing indicates and then define a larger window for areas of the product outside the standard window but are at risk for possible discontinuity. Q: My print says a dielectric withstanding test is required. It says to test to IPC-TM-650 Condition B. What is that? A: In IPC-TM-650 (Test Methods) section 5.2.1 outlines the test conditions. There are two: Condition A and Condition B. • Condition A: 500+15/-0 volts DC • Condition B: 1000+25/-0 volts DC In either case, there are two other variables considered, ramp and dwell. Ramp = time in seconds from test start to reach full test voltage Dwell = time in seconds to hold the test at test voltage. Standards are 100V/sec ramp and 30 sec- onds dwell unless otherwise specified. (Note: If no condition is specified for the test, Condition A is the default.) Q: We are testing a board that requires Class 3 electrical performance but we keep getting a few opens that will not pass at these parameters. What are my options? A: This has become a rather common question. Class 3 product does require all nets to be 10 ohms or less. However you cannot bend the rules of mathematics. In most cases even large designs will pass under Class 3 parameters, however once a single net becomes too long with regard to length of the run from end point to end point, the math just doesn't work. That is why in Table 4-1 of IPC-9252A there is a note to compensate for this. For refereeing purposes the value of 0.5 ohms per .25 mm (.984") of cir- cuit length shall apply. So if the circuit length is known, a calculation can be made for accep- tance of that net even though it does not pass at the 10 ohm stated continuity requirement. If a pass tag or pass requirement on the ma- chine is mandatory, another solution is to pro- gram the net(s) as embedded components. The calculated resistance of the long nets can be programmed in the netlist to allow the rest of the board to be tested at 10 ohms. In the end you will receive your pass tag or green light from the machine. Thank you all for reading this past year. Also, many thanks to Editors Lisa Lucke, Patty Goldman, and all the folks at PCB007 for be- ing a great team to work with! Keep the ques- tions and comments coming! Hope you all have a great rest of the Holiday Season and see you next year! PCB Todd Kolmodin is the vice president of quality for Gardien Services uSa, and an expert in electrical test and reliability issues. to read past columns, or to contact the author, click here. TesTing Todd 2015: IT'S A WRAP!

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