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34 The PCB Magazine • February 2016 duced. Many printed circuit board manufactur- ers are not able to offer the copper-filled via op- tion due to the cost of plating equipment and chemistries. The barrier to entry for these PCB manufacturers will be eliminated. The second exciting benefit to this tech- nology is the process time requirement. Solid copper-plated vias typically require 4–6 hours of plating time by the manufacturer, along with the specialized equipment and chemistry. This new product will enable PCB manufacturers to produce copper-filled vias in 60–90 minutes. A shortened cycle time will have benefits in lead time and processing costs. Product release for this screen printable paste is currently scheduled for the end of 2016. Throughout this year, pilot programs will be re- leased, further testing completed and reliability data gathered. Product Development: An Interesting Process Nano copper inks and pastes are typically sintered photonically with broadband (xenon) flash or near-IR laser. Because the copper clad- ding is too thermally conductive to allow com- plete sintering and high-power lasers are a barri- er to entry due to cost and complexity, an oven solution was sought to keep the process com- patible with existing technology. Heller Indus- tries manufactures a formic acid environment convection oven to be used for flux-less reflow. This was determined to be the perfect environ- ment to sinter nano copper without oxidation. Nano copper paste can be completely sintered in 40 minutes or less. The process development for this product has had several iterations. The initial proof of concept was to deposit paste into mechanically drilled blind vias using a vacuum bag to help fill the holes. Those initial coupons were plated and etched prior to filling to allow for laser sintering. As the development progressed, the testing moved to copper-clad PCBs with mechanical blind vias. The panels were electroless copper-plated then electroplated to simulate actual via filling require - ments. Unfortunately, the thermal conductivity of the copper foil prevented the ability to sinter the copper paste. Research then pointed to ther- mal sintering in a formic acid environment. As the development process continued, it was determined that the extended time neces- sary for formic acid sintering at 250°C destroyed the PCB laminate. Moving forward, other nano additives were included in the formulation to lower the temperature requirement to 225°C. This formulation and temperature sintered the vias completely in 60 minutes. The next phase in the development process was to screen print trace patterns on FR-4 to be sintered alongside the via-filled coupons. These samples were used to calculate bulk resistivity as compared to copper. Typical measurements were 6–8x that of bulk copper. Typical epoxy-based conductive via fills are in the 20–50x range. Today's Product Moving forward, additional product devel- opment was undertaken resulting in the cur- rent formulation, which allows the sintering temperature to be reduced to 190°C. The paste is sintered to pure copper in only 40 minutes in the Heller conveyor oven. Samples of this for- mulation were via-filled using the vacuum bag technique, on copper-clad panels, with copper- plated blind vias. The panels were Heller sin- tered, planarized, over-plated and solder float- ed. Samples were then subjected to IPC stan- dard reliability testing parameters. Each sample was floated at 288°C, held at temperature for 10 seconds, cooled, and refloated four times. The vias survived five solder float procedures. It is always exciting to learn about the new developments in products and processes for the PCB industry. In this case, incorporating nano copper inks and pastes into standard printed circuit board manufacturing techniques will al- low manufacturers to offer a solid copper-via option to their customers without significant capital investment in specialized plating equip- ment. PCB Tara Dunn is the president of omni PCB. To contact the author, or see past columns, click here. Copper via-fill teChnology in developMent