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PCBD-Apr2016

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38 The PCB Design Magazine • April 2016 JEDEC introduced fly-by topology in the DDR3 specification for the differential clock, address, command and control signals. The ad- vantage of fly-by topology is that it supports higher-frequency operation, reduces the quan- tity and length of stubs and consequently im- proves signal integrity and timing on heavily loaded signals. Fly-by topology also reduces si- multaneous switching noise (SSN) by deliberate- ly causing flight-time skew, between the address group and the point-to-point topology signals, of the data groups. To account for this skew, the DDR3/4 controller supports write leveling. The controller must add the write leveling delays to each byte lane to maintain the strobe to clock requirement at the SDRAMs. T-topology can be challenging to route, par- ticularly double T-topology with four back-to- back SDRAMs as in Figure 1, but it can be ad- vantageous when using multi-die packages. The fly-by topology used in Figure 3 is much easier to route but does not work well with high-ca- pacitance loads, such as LPDDR3 DDP (double die package) and QDP (quad die package) devic- es. IC fabricators basically arrange dies in paral- lel (as in Figure 2) to increase package density which can also increase input capacitance by up to four times. Excessive ring-back is often pres- ent in the first few nodes of the daisy chain. This is the reason why the T-topology was developed. However, if you are supporting only SDP (single die package) devices, then the fly-by by Barry Olney in-circuit Design pty LtD austraLia DDR3/4 Fly-by vs. T-topology Routing BeyonD Design Figure 1: Double T-topology for clock/address/ command/control routing. Figure 2: SDP and multi-die DDP and QDP memory devices.

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