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April 2016 • The PCB Design Magazine 75 could fill all of our needs. The three most im- portant criteria for selecting the manufacturer were their ability to support the 100A FPGA core requirement, to support the smallest de- vice pitch of 0.65 mm microvias and capping, and to build good capacitance into the board. At Adcom, we believe in embedded capacitance. Together with the PDN impedance require- ment of 0.5 mohm, we calculated and imple- mented 1 ounce and 1 mil thickness. The man- ufacturer was selected, and a stable stackup with Megtron6, DuPont HK04, and HP-Gould performance foil materials was established and implemented. The Test Flow The final phase in this feasibility project was test and integration. Here, we verified, validat- ed, measured, and analyzed the performance. To this end, a test suit was built and scripts were written. First, we tested a board only with power supplies to confirm their sequence correctness, and then the clocks for frequency, duty cycles and jitter. After verifying their functionality and programming sequences, we assembled the main components and started the bring- up phase. The CPLD loaded, and I2C interfaces were tested first, then the transceivers, followed by the FPGA, memory devices, MicroPOD and finally a load test for the FPGA device was im- plemented. Summary Being a Mentor Graphics Technology Lead- ership Award nominee is good, but being a winner is even better. Recognition for Adcom came just in time, while we were starting the next best design for 2016. The TLA contest gave us the opportunity to present our PCB de- sign team's work to the rest of the design com- munity. PCBDESIGN Ruth Kastner is COO of Adcom ltd., specializing in PCB design and manufacturability, new technologies and new materials. BehinD the scenes: aDcom's tLa aWarD-Winning Design Figure 4: HMC layer, top view.

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