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12 The PCB Design Magazine • April 2016 was true most of the time. My electronics back- ground occasionally offered some advantage, but those occasions were rare. The Seeds of Friction From the 1950s to the late 1980s, our board design methods were severely bending the laws of physics, teetering on the edge of disas- ter! A lot of today's grey-haired designers cut their teeth on the layouts of that period and got used to working without input from engi- neers. Many of those PC board designers were converted technicians, mechanical designers, and artists who learned to read a schematic and mastered artwork taping. EEs would often give their thoughts on what should be done, but you could listen to them or ignore them and the cir- cuit would likely function either way. This era created some tension between board designers and their EE counterparts, mostly because they completely ignored each other's ideas. In the early 1990s, industry as a whole started to see circuits that did not always function as in- tended or had EMI problems. By the late 1990s, this bad behavior had increased dramatically. It did not take long before we realized that poor board layout was the culprit. The layout practic- es we used for decades were no longer acceptable in many designs. We had gone from bending the laws of physics to violently breaking them. Why? ICs were getting much faster, due to output rise and fall time getting much shorter. Because of faster outputs, normal line lengths, regardless of clock frequency, were more likely to cause ring - ing, crosstalk, noise, increased EMI, etc. During this period many of the PC board de- signers who possessed little knowledge of elec- tronics grew to rely on circuit engineers to help guide component placement, since many EEs better understood which ICs and circuits were likely to cause problems. This, and the use of multilayer boards, reduced the problem for quite a few years, which gave the perception that "knowledge of circuit theory made a better board designer." Though things were better during this period, I was involved in many designs that failed EMI testing, even though the company cir - cuit engineers and I reviewed and approved the layouts. Though circuit knowledge helped us, it was not enough to stop the problems. Clearly we were missing something important! IC outputs today are so fast that the prob- lem has become an epidemic. Almost all ICs in production have rise times and fall times well under 1.0 nanosecond, mostly in the range of 300–700 picoseconds. This reality makes any transmission line (trace and its return path) lon- ger than 0.5" to 1.0" (13 to 25 mm) a potential problem. In short, everything is high-speed, ca- pable of causing SI, noise or EMI problems. All this simply means that every PC board of today has to be laid out to satisfy the laws of physics. What does this have to do with PC board de- signers and engineers working together? Both groups know there is a real possibility that each design could have problems caused by board layout. Many engineers believe their knowledge of circuit theory is the solution. Many board de- signers believe the information gained from IC app notes or eval circuits offer a solution. The fact that the two groups disagree says, "At least one party is wrong." My consulting experience has shown that, much of the time, both parties are wrong. One assumption is often made by both groups: "XYZ layout practice has always worked, so it must be right!" Well, the layouts we did in the '70s and '80s worked but they were far from right. Many circuits work but fail EMI testing, or they work initially but stop working a few years later, after ICs with faster outputs are re- leased. These issues and many others show that the layout did not properly satisfy the laws of physics in the first place. Never use past practice as proof that some method is correct! " This era created some tension between board designers and their EE counterparts, mostly because they completely ignored each other's ideas. " Working With circuit Design engineers