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82 The PCB Magazine • May 2016 (RDL) and their conductive paths with the pur- pose of rearranging the I/O pattern, e.g., from a perimeter array to an area array. These redis- tribution layers may also contain passive com- ponents. Zero level packaging processing would also include the bumping of pads which includes the deposition of under-bump metal layers (Fig- ure 1). Alternatively, the plating of copper pil- lars onto pads needs to be mentioned here. In addition, the formation of TSVs (through-sili- con vias), their metallization, filling, and inter- connect to form stacked chips, could be called zero level packaging. Furthermore, the attach- ment and removal of supporting tapes during any wafer-level operations belongs here. Figure 2 illustrates first and second level packaging. In this case, an area array flip chip (shown in upper right) is connected in first level packaging to a flip chip substrate (or package) which features a double-sided rigid core (yel- low) and two build-up layers with microvias on each side (green). This package is then con- nected to a PCB, shown on the lower lefthand side as a populated (assembled) board. Its cross- section is shown on the lower right. One can see a filled and an unfilled plated through-hole, mixed dielectric material layers (yellow and green), which is not as common as single di- electric constructions. The board also features a single microvia layer on each side. 1. Zero-Level Packaging: Material and Processing Requirements In general, wafer-level packaging uses pro- cesses and equipment that differ from the cus- tomary PCB processing equipment such as con- veyorized spray modules, automatic contact or laser printers, etc. Wafers are typically processed individually in, for example, spin coaters, "fountain platers," steppers, etc. Materials have to be compatible with such processes. Many de- position processes are vacuum processes, so that outgasing from organics can become an issue. A high degree of purity of chemicals is demanded, especially the control of ionic contaminants at very low levels. Figure 1: Bumped wafer with redistribution layers, under-bump metals and solder bump. eleCtroniC paCkaGinG levels

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