Issue link: https://iconnect007.uberflip.com/i/675678
May 2016 • The PCB Magazine 83 2. First-Level Packaging: Material and Processing Requirements Material and processing requirements of first-level packaging depend somewhat on the nature of the package, but one can point out common requirements. Soldering temperatures for connecting the chip to the package are typi- cally higher than the soldering temperature for connecting the package to the PCB. This translates into more stringent dimensional and chemical stability requirements for the materi- als that compose the dielectric layers. Since the dimensions of conductor lines and spaces are smaller than those for PCBs, the circuitization of build-up layers of flip chip packages often uses the semi-additive process which requires good adhesion of electroless copper to the dielectric film surface. In addition, the microvia dimen- sions on packages are often smaller than those of HDI boards so that drilling, copper landing- pad cleaning and hole-wall desmear are more demanding than for HDI boards. Since the first-level package is closest to the chip, near-matching CTEs (coefficient of ther- mal expansion) of all materials is desirable to avoid stress cracking during thermal excursions. The CTE of silicon is about 3–4 ppm/degree Kel- vin, for copper and for lead about 16–17; for glass weave resin about 20 in the X/Y plane, but 60–70 in the Z-axis. CTEs of 40 or less in all di- mensions are now required for dielectric layers. 3. Second-Level Packaging: Material and Processing Requirements in Comparison to First-Level Packaging There are many electrical, mechanical, safe- ty and environmental requirements for PCBs that translate into specific requirements for di- Figure 2: Illustration of first- and second-level packaging. eleCtroniC paCkaGinG levels