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68 SMT Magazine • July 2016 by Wei Keat Loh, INTEL MALAYSIA and Haley Fu, INEMI Electronics packaging technology has been relentlessly changing and pushing de- sign boundaries 1-4 , leading to adoption of new materials, assembly processes, ultra-small ge- ometries, and 2.5D and 3D integration. These changes have driven multiple assembly and surface mount challenges, and among these are concerns about package warpage. Current qualification criteria and standards are not ad- equate to predict good yield results at first- and second-level assemblies. Furthermore, measure- ment methods (dimensional and test) are nei- ther common nor up-to-date. The International Electronics Manufactur- ing Initiative (iNEMI) organized the Warpage Characteristics of Organic Packages Project to identify primary factors that can contribute to the warpage performance of selected compo- nents during typical SMT processes. The project team's plan was to define a qualification meth- od and a set of criteria (e.g., sample size, precon- dition, variations of material and processes at the first and second levels) that could be used to evaluate warpage characteristics of new and ex- isting packages in the design and manufacture of products. Their objective was to better un- derstand package warpage characteristics across different package types and attributes. The proj- ect has, to date, evaluated several types of pack- ages. This article focuses on the work related to package-on-package (PoP). PoP is widely used in mobile devices due to its integrated design, lower cost and faster time to market 5 . Understanding warpage characteris- tics and requirements of this type of package is critical to ensuring that both the top and bottom package can be mounted with minimal yield lost. The current state of PoP warpage require- ments has not been reevaluated and formed in clear specification other than customer-specific requirements. The typical SMT defect modes, such as non-wet open, solder bridging, head and pillow, and non-contact open (Figure 1) are applicable to both the joints between the PoP bottom package with the board and the PoP memory package. Other gross SMT defects can occur when there are geometry interferences between the PoP packages. This shows there is a need for ensuring that the warpage between PoP bottom and memory package is compat- ible. Efforts to leverage the warpage character- FEATURE