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PCBD-July2016

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30 The PCB Design Magazine • July 2016 by Dennis Nagle CADENCE DESIGN SYSTEMS The PCB design process has traditionally been done in silos. One group creates the design intent (schematic), another group implements the logic on the PCB, and yet another group does some checking of the design using analysis tools. This traditional approach has run into a number of problems. The first problem was that prototypes were showing up in the lab that did not work due to complicated signal and power integrity prob- lems not found by the analysis tools. But even when the analysis team equipped themselves with sophisticated analysis tools, the back-and- forth between silos or lack of time in the sched- ule tended to create chaos as design deadlines loomed. Today, modern PCB design methodology offers a more team-oriented solution. With a front-to-back constraint driven approach that enables all groups to get involved with signal and power integrity, many potential problems are either avoided or found early in the design SIGNAL INTEGRITY Tools and Design Methodology in the Modern Age process. With first order problems removed, the analysis team, with their sophisticated tools, is better positioned to focus on design sign-off so prototypes come back working the first time. This article is focused on how each part of that design team can get out of their silo and work cooperatively. Using a common constraint manager, each group can utilize their varying levels of expertise to ferret out signal and power integrity problems. Pre-Layout For teams seeking to break out of their his- toric silos, tools can help by providing a certain amount of integration. One way that can hap- pen is by having a constraint system integrated with your SI system at all stages of your design process. While decisions are being made for physical partitioning, component/IP selections, and power requirements, pre-layout analysis can help define your solution space and corre- sponding electrical constraints. This early anal- ysis as part of a well-executed constraint driven flow saves time and prevents issues from propa- gating down to SI signoff. FEATURE

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