Design007 Magazine

PCBD-July2016

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32 The PCB Design Magazine • July 2016 Topology analysis is usually what comes to mind when thinking of pre-layout analysis and is an ideal environment for what-if analysis. Here you can start from scratch or by extracting nets from design data in the schematic or lay- out. In either case you can quickly build a repre- sentation of the major interfaces in the design. Models for active devices should be as accurate as possible and interconnect can be estimated or parameterized and swept. Topologies that can be extracted from sche- matic and layout can allow all team members to access the same data for scheduling or con- straint purposes. This can also enable design en- gineers to address reflection and topology issues along with the SI engineer. The topology can be used to drive scheduling of the nets for routing and placement and capture any other relevant constraints. While a topology may be the first thing that comes to mind when thinking of pre-layout analysis, an often overlooked capability is that of virtual prototyping. This can be used to ad- dress situations where a netlist or design data- base isn't available when an SI engineer would like to create a specific prototype. Ideally, this would leverage existing design and library data for PCB layout such as stack-up, padstack, and footprints. These virtual prototypes can provide additional insight into placement and routing for simulations and constraint development that would not be possible with a topology. It is never expected to be a full representation of the design and can be extremely helpful in evaluat- ing specific interfaces. Whether topology or virtual prototype, both should be supported by structured device model management. Your SI models should get the same attention as schematic symbols and layout footprints. Analysis model management promotes reuse and saves setup time. Pre-layout analysis will identify cases where new models are needed which can then be validated and promoted to the central library. Even better is a process where the central library management system is fully integrated to include analysis models. This allows model assignments in the library data to track SI models as the design progresses from schematic to layout. Topology extraction from these design databases should support passing device models to the topologies. Floorplanning While pre-layout analysis represents a start- ing point, floorplanning is where the actual physical layout starts to take shape. Pre-netlist floorplanning is where placement and form fac- tor or other mechanical/thermal requirements are examined. But floorplanning should con- Figure 1: Pre-layout topology, with W-element and via models representing PCB interconnect. Figure 2: Virtual prototype of DDR3 interface with scheduling applied to address bus. SIGNAL INTEGRITY TOOLS AND DESIGN METHODOLOGY IN THE MODERN AGE

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