Issue link: https://iconnect007.uberflip.com/i/703122
46 The PCB Design Magazine • July 2016 shield vias near the applicable net vias and con- necting the shields to ground or power. Return path discontinuity: Signal currents always take the path of lowest impedance, cre- ating the potential for them to flow in unex- pected directions, resulting in what is called return path discontinuity. When the return path forms a loop, the result may be increased delay in signal transmission or radiation that can interfere with other circuitry in the device or violate EMC regulations. The general rule of thumb is to minimize loop areas formed by re- turn current for high-frequency signal, power and clock circuits. The SI checker identifies the target signal path, the wiring path connecting the target terminal pair, and the return path, the path closest to the target signal path be- tween driver sound ground terminal and re- ceiver side ground terminal. Next, the checker looks for an inappropriate return path, one that is not on the same layer or next layer as the re- turn path or one that exceeds the permissible distance from the return path. The rule checker then calculates the severity of the loop based on the following formula: error rating = 1 – (error path length + return path length). Impedance mismatch: Transmission lines become increasingly prone to noise as signal speed increases. In particular, mismatches be- tween the trace's characteristic impedance and the driver's output or load's input impedance create signal reflections. These reflections in turn generate negative effects including radia- tion noise. Wiring width change is one of the factors that cause impedance mismatches. The SI checker calculates the characteristic imped- ance by finding the closest reference planes above and below the circuit. Wirings in the same layer are divided into sections and calcu- lated separately when they have different refer- ence planes. High-speed signal wiring too close to the edge of a reference plane can also generate noise. The EMC advisor identifies wiring with frequency, rise time and voltage amplitude val- ues that exceed user-specified parameters. Thus, the SI checker identifies potential risks for high- speed signals that may be prone to increased ra- diation noise. Via density: If there are not enough vias distributed with sufficient density within any given area of a power or ground plane, the po- Figure 3: Return path discontinuity check. Figure 4: Trace near the plane edge. Figure 5: Plane via distribution. GETTING SIGNAL INTEGRITY RIGHT BY DESIGN