Design007 Magazine


Issue link:

Contents of this Issue


Page 49 of 73

50 The PCB Design Magazine • October 2016 tioned that the cost of development is dramati- cally reduced if simulation is employed early in the design cycle. If changes are made late in the design process, then it takes more time, people, material and therefore money to complete the project. The advantage of simulation is that it identifies issues early in the design process and rectifies them before they become a major prob- lem. Design changes that occur: • In the conceptual stage cost nothing; • During the design stage requires just a little extra time; • During the test stage means that you have to regress one stage; • During production, or worse still, in the field, can cost millions to fix and possibly damage the company's reputation. Reference designs are arguably the cause of many reliability issues. Many reference designs are developed by academics who are lacking the knowledge of DFM and reliability and have lit- tle appreciation for real-world industry expecta- tions. And although their design may work on the test bench, it may not work in an adverse environment or with a variance of vendor com- ponents where the margins become borderline. So, what are the key pillars of stability? 1. Stackup Impedance First of all, one needs to plan the most effi- cient stackup configuration for the design. For a typical digital design, 50–60 ohms of impedance is recommended. However, more than one im- pedance is generally required to convey differ- ential pairs of various technologies. Therefore, all combinations of impedances must be defined on the one substrate, which can sometimes be a difficult task unless you have the right tool. Also, dielectric materials vary in both di- electric constant and dissipation loss with fre- quency. And, although we may be tempted to use the fundament frequency of the clock as the operating frequency, the maximum bandwidth is determined by the signal rise time. An upper knee frequency of 0.5/Tr, forms a crude but use- ful translation between time and frequency do- mains. So if, for instance, the rise time is 500ps, which is typical these days, then the upper bandwidth is actually 1GHz regardless of the clock frequency. ROCK STEADY DESIGN Figure 2: Typical 10-layer stackup.

Articles in this issue

Archives of this issue

view archives of Design007 Magazine - PCBD-Oct2016