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56 The PCB Design Magazine • October 2016 Also, the same PDN connections (planes) that are used to transport high transient cur- rents are used to carry the return currents for critical signal transmission lines. If high fre- quency switching noise exists, on the planes, coupling may occur resulting in ground (sup- ply) bounce, bit failure or timing errors. Many of the failures to pass electromagnetic compli- ancy (EMC) are due to excessive noise on the PDN coupling into external cables and radiat- ing emissions. Figure 5 illustrates a PDN with optimized ca- pacitor values. This has 21 capacitors of differ- ent values and numbers to optimize the overall AC impedance. In this case, 21 capacitors from 100uF to 4.7nF are used. This approach gives a response close to the target impedance from DC to 700MHz. There are, in this case, a few anti-resonance peaks but they are way below the fundament frequency and there is very low impedance right on 533MHz. When the capaci- tor's self-resonant frequencies are spread, the parallel resonant impedance sets the limits to the PDN performance. The PDN is linked to the stackup and therefore any adjustments to the stackup configuration whether it be materials, vias or trace, clearance or thickness parameters will also be reflected in the PDN. The PDN can be fine-tuned by adding more planar ca- pacitance without affecting transmission line impedance. The optimization of the PDN is a trial and error process that needs to be done in conjunction with the stackup materials to fully exploit all avenues. It is amazing how many designers do not get the basic key pillars of stability right. For very little extra effort, your design can have improved performance and reliability over a wide range of operating environments giving you greater confidence in your products perfor- mance for the projected lifetime. Points to Remember • The impedance of the driver must match the impedance of the transmission line. • The PDN must provide low AC impedance up to the maximum bandwidth. ROCK STEADY DESIGN Figure 5: Optimized DDR3 PDN.