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SMT-Jan2017

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January 2017 • SMT Magazine 45 electronics Reliability, Vol. 49, Issue 7, 2009. 2. Karppinen, J., et al, "Shock impact reli- ability characterization of a handheld product in accelerated tests and use environment," Mi- croelectronics Reliability, Vol. 52, Issue 1, 2012. 3. Suh, Daewoong, et al, "Effects of Ag con- tent on fracture resistance of Sn–Ag–Cu lead- free solders under high-strain rate conditions," Mater Sci Eng A, Vol. 460–461, 2007. 4. Mattila, T.T. and Kivilahti, J.K., "Failure Mechanisms of Lead-Free Chip Scale Package Interconnections under Fast Mechanical Load- ing," Journal of Electronic Materials, Vol. 34, Is- sue 7, 2005. 5. Syed, A., et al, "Alloying effect of Ni, Co, and Sb in SAC solder for improved drop per- formance of chip scale packages with Cu OSP pad finish," Proc. Electronic Components and Technology Conference, 2006. 6. Roggeman, B., "Comparison of Drop Reli- ability of SAC105 and SAC305 on OSP and ENIG Pads," Unovis Area Array Consortium, 2007. 7. Mattila, T.T., et al, "The Reliability of Mi- cro-alloyed Sn-Ag-Cu Solder Interconnections under Cyclic Thermal and Mechanical Shock Loading," Journal of Electronic Materials, Vol. 43, Issue 11, 2014. 8. Zhou, T. and Fan, X., "Effect of System Design and Test Conditions on Wafer Level Package Drop Test Reliability," SMTA Interna - tional Proceedings, 2013. 9. Luan, J., et al, "Dynamic responses and solder joint reliability under board level drop test," Microelectronics Reliability, 2007. 10. An, T. and Qin, F., "Effects of the inter- metallic compound microstructure on the ten- sile behavior of Sn3.0Ag0.5Cu/Cu solder joint under various strain rates," Microelectronics Reliability, 2014. 11. JEDEC solid state technology associa- tion, "Board Level Drop Test Method of Compo- nents for Handheld Electronic Products," 2003. 12. Lall, P., et al, "Transient Dynamics Mod- el and 3D-DIC Analysis of New-Candidate for JEDEC JESD22-B111 Test Board," Proc. Electronic Components and Technology Conference, 2014. 13. Liu, F., et al, "Experimental and numer- ical analysis of BGA lead-free solder joint reli- ability under board-level drop impact," Micro- electronics Reliability, 2008. 14. Joshi, Gaurang, Arfaei, Babak, "Effect of Solder Alloy on Drop Test Performance of LGAs and BGAs," AREA Consortium Report, 2014. The research described was performed under the auspices of the consortium for Advanced Research in Electronics Assembly (AREA). This industry consor- tium was established by the Universal Instruments Corporation in the early years of surface mount as- sembly to address manufacturing and reliability chal- lenges through careful scientific investigation. With a unique operational model wherein shared research is performed on-site in the Universal process labora- tory by a professional research staff, it boasts manu- facturing scale electronics assembly tools, a full suite of analytical capabilities and a r eliability test equip- ment all run by experienced staff. The AREA consor- tium continues to stay current and relevant through the active input of its many member companies. As such, it is always open to new members with novel assembly challenges and reliability questions. Con - tact Denis Barbini at barbini@uic.com for addition- al information. Editor's note: This paper was originally published in the proceedings of SMTA International, 2016. Jim Wilcox, Ph.D., is consortium manager, Advanced Research in Electronic Assembly (AREA), at Universal Instruments Corp. Shuai Shao is currently a Ph.D. student at Binghamton University. During these experiments, he was a Graduate Research Associate at Universal Instruments Inc. Francis Mutuku is a process research engineer at Universal Instruments Inc. Babak Arfaei, Ph.D. is a materials scientist at Ford Motor Co. and a research assistant professor at Binghamton University. EFFECT OF SOLDER COMPOSITION, PCB SURFACE FINISH AND SOLDER JOINT VOLUME

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