Issue link: https://iconnect007.uberflip.com/i/770652
30 The PCB Magazine • January 2017 see an example of a buried microvia that has voided. In this example, we see that there is only an annular ring termination on layer 1. This is shown in Figure 3. In this case the electrical signature is passing through the sub- part (layers 2−19). In many cases this type of net has final terminations of the electrical net in different locations on either layer 1 or 20. This specific void may not be detected, as the landing pad on layer 1 in the example may be deemed a mid-point and thus be optimized out. This defect would be captured during functional test as that point in Figure 3 may be used as a signature validation or In-Circuit Test Point. Surface Finish With today's final surface finishes on mod- ern PCBs, the challenge for ET is to make sure defects are detected without scrapping the board in the process. While it has always been a bal- let to successfully test the circuit board without damaging it, the more modern finishes make it much more difficult. Back in the day it was just plated holes and HASL (hot air solder leveling). This is extremely robust and in the unfortunate event of significant test marks it could be run back down the line and reflowed. Today that is far from the norm. Today the most challenging finish for ET to successfully test is immersion silver. This deli- cate finish carries the high solderability char- acteristic but is usually applied very thin due to cost. Electrical test probes from either fix- ture testers or flying probes can unfortunately leave unfavorable witness marks. In the worst case, they can break through the finish expos- ing the copper landing pad below. In some cases, although rare due to via capping, these boards can be reworked. In most cases, if sig- nificant witness marks are made, the board will be scrapped. ENIG and other gold finishes take up the remainder of the surface challenges. The same hazard exists here with damage to the finish. Figure 3: Microvia barrel (outer layer). Figure 4: Witness mark 1. Figure 5: Witness mark 2. PLATING AND SURFACE FINISH: THE CHALLENGES TO ELECTRICAL TEST