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24 The PCB Design Magazine • January 2017 IPC's organization has done a fine job of bringing together manufacturing representa- tives from all over the world to discuss, define and document standards for the design and manufacturing segments of our industry. Yes, we in PCB design can perform some amazing things with today's layout tools. But we must remember not to get carried away. We must always check our settings. Remember, rarely do these settings show up as defaults in our software tools. No matter how powerful our EDA tools are, we must still make that handshake with our fel- low stakeholders—our fabrication and assembly providers. PCBDESIGN Kelly Dack, CID+, CIT, provides de- sign and manufacturing engineering services for an EMS provider in the Inland Pacific Northwest. He is also a CID instructor for EPTAC Corp. Kelly is a frequent contributor to The PCB Design Magazine and on-camera talent with the I-Connect007 Real Time video program. He may be reached at kelly@eptac.com. Figure 7: A nearly complete PCB, prior to routing. Figure 8: Example of board with tab only due to close proximity of traces. Figure 9: V-score scenario showing copper pull-back requirement at worst-case least/max material conditions. To reduce the size and increase the durability of computers, cell phones, and other data-storing devices, scientists designed a structure made of tiny lay- ers, which resembles a thick chessboard butcher-block table. Scientists grew a vertically aligned nanocomposites lattice matched on a SrTiO3 (STO) substrate using laser deposition. By control- ling the composition of the layers in the nanocom- posites, scientists can tune the degree of magnetic exchange bias coupling strength. The research team conducted a microstruc- tural analysis of the nanocomposite films using transmission electron microscopy and scanning transmission electron mi- croscopy. This new nanoscale architecture can be used for data storage in high-density memory devices as an alternative to conventional, in-plane magnetic exchange bias; such devices could pro- vide more efficient performance. Lining Up for New High-Density Memory Devices TRUE DFM: TAKING CONTROL OF YOUR EDA TOOL