Issue link: https://iconnect007.uberflip.com/i/773715
January 2017 • The PCB Design Magazine 29 Another big issue is that the designers are often not given the time to review their designs and run them through a DFM checker for spacing errors, annular ring violations, copper balance within and between layers, etc. Yes, some CAD systems have automatic design rule checking ca- pability. But when having to move larger wired areas around of facilitate new changes, they tend to turn off the automatic DRC checking. I tell designers to run their final output files through a third party DFM analysis prior to an official release. This will eliminate issues when sent out for final production. Most fabrication facilities will run a DFM analysis, prior to design release to you for little or no charge. Let's face it, when it is officially sent to the fabricator, the clock is ticking as it relates to time to market. A second mistake that is common is not understanding all the aspects of a good layer stackup. Many of today's designs contain blind and buried vias. Thus, those layers with buried vias become plated layers that often increase the layer thickness, which in turn increases the overall board thickness. This can affect the abil- ity to place the assembly into its final location. Another problem related to blind and bur- ied via stackups is determining the natural layer pairs. One must design a stackup from the in- side out. In other words, you must start with the least common denominator…an inner lay- er, then build out from there, paying attention to the naturel layer pairs that need to be electri- cally connected. Silk screen legends in component mounting holes, or on component lands. Legend inks are insulators and therefore will prevent an accept- able solder joint from forming. Data errors have diminished over the years. But they still occur. One needs to reduce the number of different files needed to build a board, while providing more sophisticated data. The best way is to migrate to an intelli- gent data format such as ODB++ or IPC-2581. These formats support data extracted directly from your CAD database, and contain all infor- mation about the design, fabrication, assembly, test, etc. Lastly, have a complete set of drawing notes and illustrations. Don't assume that your sup- plier knows what you want. State the exact material(s), line widths, spacing, non-conduc- tive coatings, protective and metal finishes. Show a fully dimensioned board outline includ- ing and cutouts or special features. Shaughnessy: Can a good (or bad) PCB design have a direct effect on downstream processes such as plating and surface finishes? Ferrari: Yes, the first is copper balance. It can af- fect the board in two distinct ways. The first is balance within a layer. Isolated conductors will etch faster than those conductors located in a dense copper area. This could result in less than minimum conductor widths in those areas. Re- member, conductor width plays a huge roll in controlled impedance designs. Isolated traces will also plate faster, and heavier than those in a dense copper area. Excessive plating could bridge closely spaced lines in dense areas. It is true that plating and etching equip- ment have gotten much better as these factors become less of an issue. But why tempt the hands of fate and leave that possibility open. Murphy's Law will almost guarantee that the issue will go against you. Throw in a properly grounded flood fill to negate the possibility of this issue occurring. The copper fill will help IN DEEP: THE ART AND SCIENCE OF DFM WITH GARY FERRARI