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PCBD-Jan2017

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42 The PCB Design Magazine • January 2017 If your designs are working well today and decoupling is not a problem, don't be com- placent. Progressive advances in the speed of digital logic will cause problems soon enough. Continual adjustment of decoupling capacitor value, package, mounting and routing rules is the only safe course of action. It is the induc- tance that limits the effectiveness of the PDN. It is very important to remember this fact. Points to Remember: • Rudimentary design rules, adequate for frequencies below 100MHz, may not be suitable for today's high-speed digital circuits. • These design guidelines recommend that the decoupling (or bypass) capacitors be placed on the bottom side of the PCB, under the BGA. • Decoupling is the process of placing an RLC network to supply the transient switching current and to provide a return current signal path back to the source. • In the critical 100MHz—1GHz band, the effectiveness of a typical decoupling capacitor is determined almost entirely by its series induc- tance. • The series inductance of a capacitor is not only determined by its ESL, but almost entirely by the layout of the capacitor's mounting lands and its associated fanout vias. • The most effective way to reduce noise is to improve the layout of the decoupling capaci- tor lands and to reduce via loop area. • In this case, the bottom mount decap has twice the loop area, for current flow, as the top mount decap which equates to about twice the loop inductance. • Same side placement, reduces the capaci- tor count from 82 (bottom mount) to just 38 (top mount), in this case, with greater band- width at half the cost and assembly time and superior performance. • For a high layer-count stackup, planes are best positioned close to the IC, with the decaps mounted on the same side, to reduce induc- tance. PCBDESIGN References 1. Barry Olney's Beyond Design columns: PDN Planning and Capacitor Selection, Plane Crazy, Material Selection for SERDES Design 2. Henry Ott: Electromagnetic Compatibil- ity Engineering 3. Howard Johnson: High-Speed Digital Design 4. All screenshots taken from the iCD Stack- up and PDN Planner software Barry Olney is managing director of In-Circuit Design Pty Ltd (ICD) Australia. The company is a PCB de- sign service bureau that specializes in board-level simulation. ICD has developed the ICD Stackup Planner and ICD PDN Planner software, which is available here. To contact Barry, click here. PDN–DECOUPLING CAPACITOR PLACEMENT Table 1: Bill of materials for bottom-mount decap vs. top mount.

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