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PCB-Feb2017

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18 The PCB Magazine • February 2017 conductors under fine-pitch grid arrays becomes increasingly diffi- cult and is effectively a constraint on package development. And power distribution into the core of the package becomes difficult and expensive. Starkey: So how does your "verti- cal conductive structures" concept overcome these limitations? Tourné: Not only can we achieve higher in- terconnection density by packing more verti- cal connections in a smaller space, at the same time we can increase conductor routing chan- nel density under grid array components. And we can do this without reducing line widths or spacings, so we can maintain high transmis- sion line speed and enhance signal integrity by better signal-to-plane reference and higher current-carrying capacity in and out of the grid array. And because we don't need to use sequen- tial build-up technology, we reduce cost. Starkey: That sounds very impressive. What are the key characteristics? Tourné: VeCS is based on special formed cavi- ties that can connect to multiple internal layers using less space than vias or microvias, leaving more room for conductor routing under area ar- ray components like BGAs. For example, a 0.65 mm pitch BGA can be successfully routed with VeCS, whereas a fan-out would not be possible with traditional vias. And VeCS causes much less disruption to ground and power planes and reference layers, which with traditional via tech- nology would be reduced to a few small slivers of copper under the BGA. At the moment, we have test vehicles in manufacturing with a 0.4 mm pitch using single lamination processes. Starkey: From the PCB fabricator's point of view, does VeCS technology require substantial capital investment or significantly different process chem- istry? Tourné: No, to both parts of the question. No direct new capital equipment is required, and the technology is well within the es- tablished capability of any high-end board shop after appropriate training and licensing. Starkey: So how do you form these cav- ities? Tourné: There are several options, but let me describe a very basic example: Drill a row of holes, in the diameter range 0.1 mm to 0.5 mm, close to- gether and separated by narrow webs of mate- rial. Remove these webs of material by drilling, routing or laser cutting, preferably on the same machine to achieve best registration. Once the structure has been formed, use standard PCB processes to clean, metallise and plate-up, then image and etch the surface conductor pattern. Finally, selectively remove copper from the plated cavity by drilling, to leave vertical copper traces where conductors are required. Perhaps a schematic diagram would help you to visualise the result (Figure 1). Starkey: So how does this compare with conven- tional through-hole interconnection? Tourné: The hole is replaced by a vertical trace or half-cylinder. The vertical trace is preferred for signal integrity performance. The structure can be filled and overplated depending on the application. More vertical connections can be created for a given surface area and, for imped- VERTICAL CONDUCTIVE STRUCTURES—A NEW DIMENSION IN HIGH-DENSITY PRINTED CIRCUIT INTERCONNECT Joan Tourné Figure 1: Schematic diagram of VeCS.

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