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PCB-Feb2017

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February 2017 • The PCB Magazine 19 VERTICAL CONDUCTIVE STRUCTURES—A NEW DIMENSION IN HIGH-DENSITY PRINTED CIRCUIT INTERCONNECT ance control, signal and ground conductors can be designed to face each other across the cavity. Another benefit is that there is no CAF path be- tween vertical traces. Starkey: You mentioned cost savings. How do costs compare with conventional constructions and where are the savings made? Tourné: The cost reduction is realised by mak- ing more efficient use of the conductor routing space and therefore reducing the layer count of the board. We offer design analysis service to demonstrate how VeCS can reduce cost in your product. With the use of more expensive mate- rials, the reduction in the BOM cost is becoming significant. In various analyses conducted last year, we have demonstrated cost reductions in the range of 15% to 40%. In future articles, we can present cases of the cost reduction analysis. Starkey: How far down the road are you with VeCS technology? Tourné: We've progressed a long way since demonstrating the initial proof of concept, and we continue to work closely with leading OEMs and fabricators. One manufacturing ex- ample is a 12-layer test board, 2.2 mm thick, on MEGTRON6, with 0.5 mm, 0.75 mm, 0.8 mm and 1.0 mm BGAs routed on the same panel. We have subjected samples of this construction to six reflow cycles at 288°C, and found no evi- dence of interconnection failure. Results after six solder shocks at 288°C were similar (Figure 2). And we have taken daisy-chain test panels through multiple reflow cycles followed by ther- mal cycling to failure, with results comparable with through-hole examples. Regarding imped- ance control and signal integrity, I can show you some remarkably good TDR traces from the area under the BGA. Starkey: What about design? Do any of the major CAD vendors offer the capability to generate de- signs based on VeCS technology? Tourné: At the moment, we have two CAD software houses working on the technology and they have demonstrated capability already. Figure 2: Cross-section of the interconnect with the innerlayer. Figure 3: Board with daisy chain on 1.0 mm pitch using VeCS technology used for reliability testing of the interconnects. The fabrication and testing is done by WUS.

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