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24 The PCB Design Magazine • February 2017 Generally, PI engineers communicate with PCB designers by email, phone calls, or meeting face to face to discuss the issues and the solu- tions to fix problems with the layout. Unlike when analyzing signal integrity, PI engineers are not usually involved in the early stages of the design because of the lack of pre- layout analysis tools for power analysis in the industry. The first cut of PCB power design usu- ally is based on experience and industry con- ventions, so many power problems only surface late in the process, leaving PI engineers to focus mainly on the post-layout verifications for pow- er systems. Also, PCB designers generally do not want to use professional analysis tools because of their complicated settings and different EDA tools/platforms. This lag time greatly affects the efficiency of design and the time-to-market of the products. PI-Aware PCB Design Methodology To solve these challenges, a new design methodology is needed for PCB power design that combines the design and analysis together. The workflow of this methodology is shown in Figure 1. With this methodology, PI engineers are in- volved in the design process at very beginning of the design process, in the schematic design stage. They can prepare the component mod- els, settings, and constraints for component instances, and for the entire design when the schematic is complete. These settings and con- straints are one-time efforts, and they can be passed to layout automatically for future post- layout analysis. PCB designers can complete the setup for simulation quickly by clicking few buttons; they do not need to understand all the ins and outs of complicated analysis concepts and parame- ters. All violations are recorded in an HTML re- port and can be noted in the layout. With cross- probing between the report and the layout, PCB designers can locate the problems quickly and accurately, and fix them directly. To verify the effects of the layout changes, a single click re- runs the simulation with a refreshed report. The same engine is used as the power expert, so the simulation results are consistent. All engineers—including hardware engi- neers, PCB designers and SI/PI experts—can use the same platform for design and analysis, and all settings in the pre-layout simulation can be reused by the post-layout analysis. New Technologies Some new technologies introduced in this new methodology support the analysis-fix- analysis process include Analysis Model Man- ager (AMM), Cadence Allegro PowerTree tech- nology, IPC-based constraint generation, inte- grated design/analysis environment and so on. These technologies enable designers to set up automated analysis, making their process much simpler. In the early stages of design, PI engineers can create a PowerTree flow with the schematic data. If available, AMM data can be applied to the PowerTree flow, as well. Based on the Pow- erTree flow, the PI engineer quickly generates a workspace that includes all component settings, constraints, and relevant power/ground nets for enabling and selection. In the layout stage, PCB designers can use the workspace for an iterative analysis-fix-anal- ysis process without special support from PI ex- A NEW POWER DESIGN METHODOLOGY FOR PCB DESIGNS Figure 1: Advanced PCB design/analysis flow.