the PCB Magazine

PCB-Apr2017

Issue link: http://iconnect007.uberflip.com/i/808383

Contents of this Issue

Navigation

Page 61 of 95

62 The PCB Magazine • April 2017 more common test methods are: IPC-TM-650, method 2.6.7—Thermal Shock & Continu- ity, Printed Board[2] and IPC-TM-650, method 2.6.7.2—Thermal Shock, Continuity and Mi- crosection, Printed Board[3]. Each of these methods, and others developed by committee members within the IPC-TM-650 test methods manual, pair the thermal shock exposure with some type of analytical testing to allow for an evaluation of the PCB's ability to withstand the stress. Anyone who has performed or contracted thermal shock testing knows that the process can be drawn out. As mentioned earlier, the exposure is certainly not complicated; how- ever, the laws of thermodynamics can only be "pushed" so much as thermal mass and heat transfer limitations can greatly lengthen a given thermal shock test. As an improvement on this drawn-out test protocol, a technology referred to as HATS (highly accelerated thermal shock) was devel- oped. The idea behind the advancement was to speed up the traditional thermal shock test by decreasing the time needed for the test samples to reach the desired temperature extremes. Spe- cially designed test coupons are needed, which could be a deterrent for those that would prefer to test their actual product; however, they are necessary for the equipment's setup and, ulti- mately, to achieve the faster test time. In the end, the idea of thermal shock testing is not new and the exposures themselves are all fairly similar across all the various test method- ologies. Further, advancement in the test the- ory has been minimal over the years given its simplistic nature, other than the development of HATS testing which also has its detractors. Ultimately, the "during" or "pre/post" exposure evaluation is the truly critical part of this realm of testing. Being able to detect, locate, and then understand any failure that you've experienced as the result of the testing—that is of real ben- efit to the tester. And this sentiment holds not just for PCB test samples, but for any type of test specimen that is exposed to thermal shock test- ing. If there is no metric that your test sample is being held accountable to, then why did you perform the test to begin with? PCB References 1. Department of Defense Test Method Stan- dard: MIL-STD-202 2. IPC-TM-650 Test Method 2.6.7A 3. IPC-TM-650 Test Method 2.6.7.2B Keith M. Sellers is operations manager with NTS in Baltimore, Maryland. To read past columns or to contact Sellers, click here. YOU'RE IN FOR A (THERMAL) SHOCK! Conventional copper electronic interconnect faces fun- damental obstacles that prevent it from meeting increas- ing bandwidth demands. Optical PCB technology had been researched for several years, but significant issues remain before it can be commercialized. The HDPUG Optoelec- tronics project set out to demonstrate that optical wave- guides incorporated within a backplane could benefit the system's interconnect topology. HDPUG facilitator Jack Fish- er explains that a demonstrator has now been built and is currently under test at a number of leading OEMs. Click here to view the interview. RTW IPC APEX EXPO: HDPUG's Jack Fisher Discusses Updates on Optoelectronics Project

Articles in this issue

Links on this page

Archives of this issue

view archives of the PCB Magazine - PCB-Apr2017