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PCBD-June2017

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36 The PCB Design Magazine • June 2017 Note: Part 1 of this column appeared in the June 2017 issue of The PCB Magazine. Technology and processes for embedding capacitor and inductor elements rely on sev- eral unique methodologies. Regarding provid- ing capacitor functions, IPC-4821 defines two methodologies for forming capacitor elements within the PCB structure: laminate based (cop- per-dielectric-copper) or planar process and non-laminate process using deposited dielectric materials. Distributed (planar) Capacitors Considered the simplest solution and com- monly used to replace discrete power supply de- coupling capacitors the planar capacitors utilize closely spaced power and ground planes sepa- rated by a thin dielectric layer. The dielectric can be a layer of the glass-reinforced epoxy ma- terial, a thin layer of non-reinforced polymer, or a polymer sheet material filled with ceramic powder. This technique will provide significant capacitance and delivers very low inductance. The capacitance range for planar capacitors is 1pF to 1mF, dependent on the dielectric con- stant, material thickness and area. Because the planar capacitance is propor- tional to the dielectric thickness between the power and ground planes, thin dielectrics are preferred. This will increase planar capacitance while reducing planar spreading inductance and minimizes overall board thickness. The reduc- tion of planar spreading inductance also results in a lowering the impedance path while increas- ing the effectiveness of discrete capacitances. The total capacitance of the power and ground pair is determined by the effective com- by Vern Solberg Embedding Components, Part 2 FEATURE COLUMN: PCB DESIGNERS NOTEBOOK

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