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38 The PCB Design Magazine • June 2017 mon (overlapping) area of the copper electrodes. This area, times the capacitance density, repre- sents the total capacitance. The following is the equation recommended for modeling planar capacitance: Where: C = Capacitance (Farads) A = Area of plates Dk = Dielectric constant of material between plates K = Constant t = Thickness between plates For example, if the effective area of the ca- pacitor electrodes is 1000 cm 2 and the capaci- tance density is 700pF/cm 2 then the total effec- tive capacitance is 0.7μF. If an additional pair of planes is incorporated in the design, the total capacitance can be 1.4μF. The same logic is used to determine the size of discrete filter capacitors built within the distributed plane. Polyimide (PI) Film Capacitors The PI distributed planar capacitors value is calculated by both PI area and thickness. Poly- imide film capacitors are typically used to lower the impedance (due to low inductance) of the PCB portion of the power distribution network and the removal of most, if not all, decoupling capacitors of 0.1 μF or lower value. For example, OAK-MITSUI furnishes the fol- lowing formula for estimating capacitance of a distributed planar capacitor using their PI film dielectric: • 12 μm thick material furnishes 140pF/cm 2 • 16 μm thick material furnishes 230pF/cm 2 • 24 μm thick material furnishes 310pF/cm 2 Deposited Dielectric Capacitors Dielectric materials that are supplied in the form of paste, liquid, powder, or precut vapor deposited sheet material. These materials can be applied within the layer structure of the PCB us- ing a screen-printing, deposition or lamination. The capacitor dielectric requires two conduc- tor planes using the copper foil of the PCB or other conductive material that are applied over the dielectric element by screen-printing or ad- ditive plating. For example, screen-printing techniques are commonly used to apply poly- mer thick film (PTF) and ceramic-filled polymer (CFP) dielectrics onto an etched copper pattern followed by screen printing of a conductive (sil- ver-filled polymer) material over the dielectric to form the second termination. The capaci- tance range for the PTF and CFP composites is only 1pF to around 10pF. Ceramic Thick-Film Dielectric A variety of capacitor designs may be fur- nished using the thick-film ceramic (CTF) paste on copper foil process. The dielectric material is applied over a thin pre-conditioned copper foil. The ceramic paste contains ferroelectric Ba/TiO (barium-titanate) powder and a glass powder to facilitate screen-printing. The manufacturer states that one-ounce copper foil is preferred for handling and foil stability during the firing process. In preparation for applying the ceramic coating, a very thin mixture of copper and glass paste is preprinted onto the copper sheet mate- rial. The preprint acts as an adhesion promoter for the dielectric layer. The preprint can be ap- plied in a pattern that is slightly larger than the subsequent dielectric layer or it can cover the entirety of the copper foil. Firing of the ceramic material is accomplished in a nitrogen furnace at approximately 900ºC. Ceramic dielectric may completely cover the copper foil or it may be ablated to cover only selective areas. The value range for the CTF coated foil is 1pF to around 10nF, dependent on the dielectric constant, ma- terial thickness and area. Ceramic Filled Photo-dielectrics CFP materials enable creation of a capacitor structure near the outer-layers of the printed board. CFP embedded capacitors developed by Motorola Labs and Vantico AG are also based on barium-titanite composition with a dielec- tric constant of approximately 20, which limits the capacitance density to a few nF/in 2 . The tar- get of the development was to create a material that would provide a capacitance density of 10 EMBEDDING COMPONENTS, PART 2