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PCBD-Aug2017

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44 The PCB Design Magazine • August 2017 to some extent, by improving the layout and routing, reducing the number of loads and/or adding terminators. Secondly, IC manufacturers are not always doing us a favor when they begin shipping "new and improved'' logic circuits. When substituted into a legacy design, the in- crease in speed may buy nothing but headaches. From the perspective of an IC manufac- turer, shrinking a die is a winning proposition because the new chip is almost certain to meet or exceed its published specifications at a lower cost. However, from the perspective of the de- signer, shrinking a die, in an existing product design, can be a daunting prospect, because the new rising and falling edges are almost certain to switch considerably faster. Faster edge rates mean reflections and sig- nal quality problems. So, even when the pack- age hasn't changed and the clock speed hasn't changed, a problem may exist for legacy de- signs. The enhancements in driver edge rates have a significant impact on signal quality, tim- ing and crosstalk. This also has a direct impact on radiated emissions. Figure 2 shows the massive increase in emis- sions from the slowest to the fastest rise time previously discussed. When dealing with sub- nanosecond rise times, the emissions can eas- ily exceed the FCC/CISPR Class B limits for an unterminated transmission line. The ratio of signal rise time to physical de- lay of an interconnect determines how the cir- cuit behaves. A small ratio, meaning a short rise time compared with the innate time delay of the interconnect, produces distributed be- havior. Whereas a large ratio invokes lumped- element behavior that requires little attention. When considering any aspect of your circuit geometry, the relationship between physical size and rise time determines the relative im- portance of that object in the overall scheme of the circuit. The signal rise time, rather than the signal clock frequency, determines the critical signal speed. Basically, any rise time of 1ns or less may be of concern. An ideal square wave clock signal with the spectrum of a 50% duty cycle, and a zero pi- cosecond rise time, has frequency components (harmonics) only at multiples of the clock fre- quency. The Fourier Transform converts a time domain waveform into its spectrum of sine wave frequency components. The amplitude of the even harmonics is zero, as they cancel out in the Fourier Transform due to the even mark- to-space ratio. The amplitude of the odd har- monics is given by: where n is the odd harmonic number For example, the amplitude of the 1 st har- monic, where n = 1, is 2/(3.14 x 1) = 0.64V. The amplitude of the 3rd harmonic, n = 3 is 2/(3.14 x 3) = 0.21V. The amplitude of each harmonic WHEN LEGACY PRODUCTS NO LONGER PERFORM Figure 2: Radiated emissions from the 30ns edge rate (left) and 1ns (right).

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