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PCB-Oct2017

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20 The PCB Magazine • October 2017 cess takes a further skim of copper from both the height and width of the tracks. There are some fail-safes to try to help us with the above problems. Automatic optical inspec- tion can certainly check for over-etched panels, but in truth the capability is very limited. Nearly every machine is only able to access the width of the top surface of the track which leaves a signif- icant open question about the shape of the side- walls of the tracks. Undercut of the copper due to over-etching may not be apparent at inspec- tion but it can significantly reduce the cross-sec- tional area of the conductor. There is also no way to be sure of the actual copper thickness re- maining without a destructive microsection be- ing taken—and there is no guarantee that every panel is the same as the next anyway . The outer layer process is like the innerlay- er process in so much as there are plenty of opportunities for variation—especially due to copper thickness variation through the plating process. We end up with a finished panel which potentially has quite a lot of variation in the cross-section of its conductors. All of the in- spection processes have passed and been de- clared within tolerance but the variation is still there. For signal integrity, this variation can be quite a headache. It is possible to measure the variation with a high specification flying probe test which can test the exact resistance of ev- ery conductor, but this is a long and expensive way to test a panel. You can reduce variation by demanding than no re-processing of mate- rial is allowed at any time but there is a poten- tial cost implication for this approach. If your one in 50 panels is particularly un- lucky it may get hit hard at every stage of the process. This worst-case scenario can lead to some disappointing results when the product is populated with components and product testing commences. So far, all the points raised here have relat- ed only to the most basic of parameters which could affect signal integrity. Higher and high- er signal speeds mean that the bar is constant- ly being raised with regard to reducing pro- cess variation. At the highest signal speeds, the smooth finish of the copper becomes a signifi- cant factor to ensure performance of the circuit. The so-called "skin effect" reduces the speed of the signal as the surface of the copper becomes rougher. At a couple of the normal manufactur - ing stages we went out of our way to roughen the surface of the copper to ensure good adhe- sion. The stronger the treatment of the copper, the worse the signal speed becomes. Adhesion against signal speed—two target conditions that are in significant conflict with each other. If you are a buyer or user of circuit boards, this may give you some idea of why there can be significant variation in circuit performance when you compare products from different fab - ricators. It is not necessarily a reflection of any- one doing anything wrong, just manufacturers working within the allowed parameters. In adversity , there is often opportunity and I am pretty sure this is the case with high-speed signal transmission within circuit boards. Mate- rial suppliers are working hard to ensure their side of the copper has the required finish. Good fabricators will do their best to find ways to achieve the same. This market requires consis- tency from batch to batch to make sure that the end-product performs as required. If you can fulfill the brief your factory is likely to be busy for a little while. PCB Marc Ladle is director at Viking Test Ltd. To contact Ladle or to read past columns, click here. FABRICATING FOR SIGNAL INTEGRITY " The outer layer process is like the innerlayer process in so much as there are plenty of opportunities for variation—especially due to copper thickness variation through the plating process. "

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