The PCB Design Magazine

PCBD-Oct2017

Issue link: http://iconnect007.uberflip.com/i/886239

Contents of this Issue

Navigation

Page 35 of 87

36 The PCB Design Magazine • October 2017 Causal and frequency-dependent mod- els and simulations are important for today's high-speed signal integrity simulations. But are causal models also necessary for power integ- rity simulations? When we do signal integrity eye diagram simulations, we define the source signals, so if we use the correct causal models for the passive channel, we will get the correct waveforms and eye reduction due to distortions on the main path and noise contributions from the coupling paths. The details of the simulated waveforms will make a difference in the accuracy of the eye clo- sure; in such cases the causality of the passive component models is important. At the other end of the spectrum, when we do point-of-load PDN simulations, causality today is much less important, not because we don't care for the ac- curacy of the result, but primarily because the excitation signal, the signature of the current demanded by the load as a function of time, is usually not known very well. One of the areas in between, which involves PDN models and requires good causal models is when we do SI- PI co-simulation. For instance, when we want to simulate the eye closure due to simultaneous switching noise and PDN noise on memory sig- nals, the memory excitation signals are set by us and therefore it makes sense to use good causal models for the PDN to get accurate results. This article shows you a few important points how you can achieve it. For any interconnect, which has non-neg- ligible delay for the particular application (in technical terms: which is not electrically short), we need to use a simulation model that de- scribes not only the interconnect impedance, but its propagation delay as well. Extrapolat- ing from the world of lumped circuits, cascaded segments of series inductance and parallel ca- pacitance is a simple and brute-force approach to model both impedance and delay. A simple ladder circuit shown in Figure 1 can be used to simulate the approximate behavior of package pins, connector pins, traces and cables. This model represents a lossless intercon- nect with 50-ohm characteristic impedance and 150 ps delay in each segment, a total of 450 ps delay for the three cascaded segments. The model works well if the equivalent rise time of the signal we want to pass through this circuit is much longer than the delay in one segment. If all what we want to accurately simulate is the rise time of the signal passing through this cir- cuit, this ratio can be as low as three to four. If we need good accuracy of the entire waveform, by Istvan Novak ORACLE Causal Power Plane Models FEATURE COLUMN: QUIET POWER Figure 1: Ideal one-dimensional LC ladder.

Articles in this issue

Archives of this issue

view archives of The PCB Design Magazine - PCBD-Oct2017