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48 The PCB Design Magazine • October 2017 has been used to create hundreds of IBIS- AMI models for systems designers to use with their design simulations. At these frequencies, both ISI and loss are signifi- cant impairments, and the energy from a specific transition can affect the sig- nal at the receiver from before the main body of signal itself arrives and for many unit intervals (UI) afterwards. Millions of bits need to be simulated to properly eval- uate channel behavior, which is why IBIS-AMI has supplanted traditional SPICE methods for serial link analysis. AMI assumes that the I/O buffer analog models are linear and time invariant (LTI). The interconnect be- tween the buffers is also LTI, which means the combination of the analog I/O and channel can be characterized using circuit simulation techniques and then combined with equaliza- tion models to predict the overall link behavior. The AMI models describe transmit (Tx)/receive (Rx) equalization behavior and are supplied as executable models in the form of dynami- cally linked libraries (DLL in Windows, shared objects in Linux) that are linked directly into EDA simulators at simulation runtime. The IBIS Open Forum is the industry organization re- sponsible for the management of the IBIS-AMI specification. These executable models there- fore model the detailed equalization behaviors of both the transmitter and receiver, while pro- tecting the device manufacturer's IP because they are supplied as executable code. AMI mod- els can be used to do two different types of sim- ulations: statistical and time domain. Statisti- cal simulations can predict the performance of simulations for essentially all possible patterns. Time domain simulations can more accurately handle non-linear and adaptive behavior in the buffers, but are typically limited to simulations that are 10 million UI long. Shaughnessy: How would AMI models be used to model DDR5 topologies? Katz: Serial channels are differential, point to point topologies with the clock embedded as part of the signal, while DDR5 channels are single ended, multi-drop topologies that use separate signals for data and the strobe (clock) signal used to sample the data. So, while we can apply AMI techniques to DDR5 analysis, we need to pay care- ful attention to the differences between the original applications of AMI modeling and how we apply those techniques to DDR5 applications. In its simplest form, we could approach DDR5 modeling with AMI the same way we approach serial channel modeling: charac- terize the analog channel, derive an impulse re- sponse and then process it with the algorithmic models to determine the effects of equalization. We simulate the analog channel in SPICE with a small rise time step to extract a step response with adequate resolution, then differentiate that to create the impulse response we need for algorithmic processing. However, we should note that IBIS-AMI cur- rently uses a single impulse response to model the channel, which is a good assumption for long serial channels with balanced drivers. With shorter channels, signal-ended signaling and rise/fall asymmetries we see in DDR5 ap- plications, we'll have to see whether differences in rising and falling edges will be adequately de- scribed by adding impairments to the analysis such as jitter and adjusted eye masks or whether we need to characterize rising/falling responses separately. If we need to derive separate impulse responses for rising and falling edges, that will drive a lot of additional complexity into the IBIS-AMI specification and the analytical pro- cess. Shaughnessy: So, AMI models were originally developed for serial channels. How do they compare to DDR5 topologies, and how does that matter from an equalization standpoint? Katz: Serial channels tend to be long and lossy, while DDR channels tend to be short and re- flective by comparison. The development of se- rial channel equalization techniques has most- ly focused on overcoming loss. TX FIR and RX CTLE filters, the first two types of equalization used for serial channels, are designed to com- pensate for high frequency loss in the channel. SISOFT PREPARING FOR DDR5 SIMULATION NEXT YEAR Walter Katz

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