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54 SMT Magazine • November 2017 The void acceptance criterion is ill defined and strongly tied to void locations, volume and size. In addition, void acceptance is largely a function of a product's end use—Class 1, 2 or 3? And, to make it worse it's important to under- stand what type of component the solder joint in question is attaching to the circuit board (e.g. BGA, micro BGA, LGA, CSP, QFP, QFN, QFD, DCA, passive devices, etc.). What about stacked memory modules? Add to that, how are we measuring a solder joint's void population and character? 2D, 3D? And, of what can be thou- sands of solder joints on a circuit board, which ones do we inspect? All of them? No, that's time prohibitive. Then how many and which ones should we look at? Now, if you think this is a knotty issue for an OPD who assembles the products they design, pity the poor EMS. They build other compa- ny's products. Does their ODP customer bring a void spec to the table? Is it a requirement of the purchase order? Do they invoke the require- ments of joint standard IPC-STD-001, which in turn invokes the requirements of industry stan- dards—IPC 610 and IPC 7095? Or, do they look to their EMS for guidance on voiding accept- ability? If the product fails in the field because of a solder joint that has fractured, who carries the liability? Who underwrites the cost of establish- ing root cause for the failure? Void Reduction at SMTA International This column is being written a few weeks after this year's SMTA International in Chica- go. I hope many of you had the opportunity to attend the conference. In lieu of a more re- sponsive and timely post-secondary education- al system, this annual event brings leading edge issues and production equipment to the at- tention of our real world electronic product as- sembly community. At the conference I chaired a technical ses- sion entitled "Void Reduction." Here is the ses- sion description: This session presents three papers that docu- ment the results of solder joint void studies. All three studies were performed to establish the caus- al relationships that exist between material selec- tion and process environment variables and the reduction in solder joint voiding. The first paper addresses the effect of solder reflow environment, paste printing material and printing process vari- ables. The second is the third part in a series of pa- pers on voiding. It provides the results of a para- metric study conducted to examine void reduction as a function of paste powder size, solder alloy and PCB surface finish when using QFN, BGA and LGA components. The third paper describes a new process technique that applies sinusoidal vibration to the circuit board during solder joint formation in order to reduce voiding. 6,7,8 I think it is significant that there were no papers that addressed what is an acceptable lev- el of voiding based on empirical testing or an- alytic study. There was no session entitled "Ac- ceptable Voiding." However, I believe IPC has a working committee that is tasked with updat- ing the current industry specs. The message in the "Void Reduction" session as it was described in last month's SMT Magazine, "Achieving the Perfect Solder Joint," do everything possible to eliminate or at least minimize voiding. "Acceptable" voiding is left to specifica- tion organizations and colleagues that have at- tempted to quantify the issue. 9,10 Most of these have focused on voiding in BGA solder joints. So, let's eliminate voiding. Cost Consequences What is the cost? I remember the "zero de- fect" obsession. A zero-defect rate for products being shipped is certainly a justifiable and nec- essary production requirement. However, in- process zero defects? Even a 6-sigma defect pro- THE PROPER POSITION TO TAKE ON VOIDS IN SOLDER JOINTS, PART 1 " Now, if you think this is a knotty issue for an OPD who assembles the products they design, pity the poor EMS. "

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