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PCB-Nov2017

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34 The PCB Magazine • November 2017 As hand-held and portable electronic prod- ucts and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional print- ed board fabrication and what's commonly re- ferred to as high-density interconnect (HDI) processing. The primary driver for HDI is the in- creased complexity of the more advanced semi- conductor package technology. These differenc- es can be greater than one order of magnitude in interconnection density. Semiconductor Packaging Although the development of array-con- figured packaging for ICs has alleviated circuit routing difficulty somewhat, product minia- turization and performance goals are not easi- ly achieved. To further complicate the PCB de- sign process, many companies furnishing mul- tiple die or multi-functional semiconductor packaging are forced to significantly increasing I/O while reducing both contact size and pitch. This higher I/O and finer pitch evolution is due in part to the OEM need for more capability in an ever-shrinking space. Further complicating traditional PCB design, some companies are do- ing away with some or all traditional semicon- ductor packaged semiconductors. System-in-package (SiP) for example, wheth- er die stack or package-on-package, has rapidly penetrated most major market segments. This includes consumer electronics, mobile, auto- motive, computing, networking, communica- tions, and medical electronics. The benefits of SiP will differ for various market segments but they can share some very common elements: shorter time to market, smaller size and low- er cost. Area efficiency (more functionality in a single package footprint) has resulted in the strongest initial penetration in consumer elec- tronics. These mixed function SiP solutions have become commonplace in small form fac- tor systems, such as mobile phones, memory cards, and other portable electronics products and the number has been increasing rapidly. In contrast, it has become common for developers to procure bare, uncased die ele- ments that are configured for facedown (flip- chip) mounting. Although flip-chip was origi- nally considered for relatively low I/O die, the redistribution of the peripheral located con- tact sites to a more uniform area array format Strategies for High-Density PCBs FEATURE COLUMN: DESIGNERS NOTEBOOK by Vern Solberg

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