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58 The PCB Design Magazine • November 2017 Current high-speed PCB interconnects ex- hibit the following issues: 1. Limited current carrying capacity. This is basically due to the trace width–3 to 7 mils is the typical range. That is, a signal carry- ing circumference of 6 to 14mil for stripline and half that for microstrip, without including the sidewall and current crowding. Current crowd- ing, due to the skin effect, reduces the effective capacity by limiting flow, to the outer surface, regardless of the copper thickness. 2. High dielectric loss of the substrate material. Standard high-speed materials are too lossy however, a more homogeneous, ultra-low loss dielectric solves this problem. Although, the current costs are prohibitive, compared to com- monly available dielectric materials, this is like- ly to come down as the industry accepts them as being necessary. 3. The copper surface is too rough which increases resistive loss. At high frequencies, the effective resistance of the copper increases relative to the addition- al distance over which the current must trans- verse the contours of the surface. This can be alleviated by using smooth copper. However, the copper foil is produced smooth and then roughened purposely, in two stages, to prevent de-lamination. 4. The signal data transfer capacity is limited by distributed losses. Pragmatic effects, such as frequency depen- dent losses, come into play at clock frequencies above 1GHz. They are of concern for fast rise time signals, with long trace lengths, such as multi-gigabit serial links. This frequency depen- dence causes rise time degradation and reduces the upper bandwidth, of the signal, resulting in reduced channel data transfer. Substrate inte- grated waveguides can be used as an alternative to improve the bandwidth however, the transi- tioning from the familiar microstrip or CPW to a SIW can be a challenge. Similar to the signal propagation character- istics of the traditional waveguide, the electro- magnetic wave in a SIW also moves forward, reflected along a zigzag route between the two fences of vias. Since the vertical metal walls are replaced by PTH via fences for the SIW struc- NEXT-GEN PCBS—SUBSTRATE INTEGRATED WAVEGUIDES Figure 2: Fundamental mode SIW cross-section (top) and waveguide electromagnetic field (bottom).

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