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12 DESIGN007 MAGAZINE I MARCH 2018 the end of a design cycle. And obviously, that's where no one wants to be. Everyone is always running out of time, and there is almost never enough time to perform optimizations or a cost reduction. PI engineers barely have enough time to perform a signoff analysis to judge "pass or fail." What we've really tried to do over the past two years is what my colleague Brad Grif- fin likes to call "shift left." That is, how can we move any type of analysis earlier—to the left—into the design cycle? Here is one exam- ple from a schematic point of view: Do you have enough decoupling capacitors on a rail? Do you have the correct decou- pling capacitors on a rail? Most schematic designers today cannot answer those questions. Our goal has been to take what has histori- cally only been done at the end- of-design cycle, a PI expert with barely enough time to do a check, and enable design engineers and layout engineers to assist much earlier. How can they participate? Dack: Upstream, to me, is meaning at possibly the schematic level. Chitwood: Yes, the goal is enabling schematic designers from the very beginning. This person needs an automated way of putting together something that is very simple and very quick but gives useful and actionable information. For example, have the correct decaps been selected? The schematic designer needs that information at the beginning, rather than have the PI expert at the very end say, "Oh, well, you had the wrong decaps all along." Now you have to go back and rip this out, and it can be as bad as literally starting over from your power delivery routing point of view. Obvi- ously, that's tremendously expensive. Dack: For the novice out there who might not be as educated in simulation as they may want to be, explain some of the elements of simula- tion, as far as parts and data sheets and what results we're looking for. Chitwood: There is a great example of what we envision a layout designer being able to do who may be a novice at simulation. There are PDN inductance checks that we have made very easy to access. Absolutely no electrical models are required. All you need is the lay- out database with the correct stackup and the power net name of interest. With this informa- tion, the tools can automatically identify the component names and where they are placed. With respect to the IC device, we solve the loop inductance between the IC and each of its decaps. The objective is simple and the results are intuitive: Identify any decaps that are outli- ers. With specific problems iden- tified, the layout designer can investigate if something has been improperly routed or if any decaps have been placed too far away. If so, do they need to be moved or switched from a top layer to bottom layer, for example. These problems can be quickly identi- fied and corrected up front. Dack: Upfront meaning not at the schematic level, right? Chitwood: Correct, that example is for the lay- out designer. Now, let's shift-left to the sche- matic designer. As I alluded to earlier, the sche- matic designer needs to know what selection of decaps to choose fr om day one when no layout is available. What enables this flow is a PDN's target impedance. For an IC vendor that is pro - viding a chip to a systems customer, we are advocating for these suppliers to also provide a target impedance so that the schematic designer can design to a specific level of pass-fail perfor - mance. Because without target impedance, the schematic designer is fundamentally stuck in a "better or worse" situation, where the designer says, "I can keep adding decaps, and I can con - tinue making performance better, but when do I quit?" Without target impedance, there is no way to truly know when you are finished, no way to know pass or fail. This situation usu - ally leads to significant decap overdesign and unnecessary BOM costs. Sam Chitwood

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