Issue link: https://iconnect007.uberflip.com/i/952929
MARCH 2018 I DESIGN007 MAGAZINE 13 Dack: Yes. We get a target impedance, and we're using the tool up front at the schematic level. At what point can we determine if add- ing extra plane layers will enhance power integrity? Help us out. Tell us how the tool is used for determining stackup and planes. Chitwood: For PDN stackup design, it's a great in-between area, between schematic and lay- out. We refer to this as pre-layout for a PDN. Dack: Because we can add a layer just like that. How do we know how much that's going to help us to cost-justify for this? Chitwood: PDN pre-layout is one of the work- flows we have created to help guide users through selecting stackups and choosing PDN layer assignments. Performance can drastically differ whether you put a power plane near the top or bottom of a stackup, and whether you put decaps on the top or the bottom surface. Those are critical decisions that simulation can automate and also yields decap placement guidelines. Do not consider these results as mandatory decap placements at this stage, but as analytically-based suggestions. Three lists of decap recommendations are provided: decaps for the top layer, bottom layer, and underneath the device on the backside of the board. Given these three spreadsheets of pre-layout decap placement guidance, the layout designer now knows exactly what to implement. This guid- ance is tremendously better than the previous rule-of-thumb guidance of "place decaps as close as you can to the device." Dack: This gives the layout designer something to shoot for based on other target parameters in the design. For instance, a lot of designs are driven to strive for a single-sided assembly, so the designer will know the cost, already knows the cost of adding components and capacitors to the back side of the board as sole parts. But will he also know the performance gains and may become able to make a cost analysis? Chitwood: Absolutely. One of the unique capa- bilities of our tools is the ability to include cost information as part of the decap optimization. It's not common, in these type of engineering tools, that you can study the tradeoff between electrical performance versus BOM cost. We can include the per-component cost, the assembly cost, and what is sometimes referred to as a BOM penalty cost (or the cost to stock that component during assembly). Dack: A lot of the conversation among the attendees at this show is talking about high- speed and signal integrity issues, but we also have designers who are dealing with all the "design fors." We have "design for cost" parameters now. We have "design for manu-