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Design007-Mar2018

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46 DESIGN007 MAGAZINE I MARCH 2018 • It does not matter where an AC coupling capacitor is placed along the transmission path. • The capacitor transition is critical: how low the reflectivity is, and whether it is placed near other channel discontinuities. • AC coupling removes the common mode level and allows the receiver to set its own bias point. • To eliminate the excess parasitic capaci- tance, associated with surface mount lands, a portion of the reference plane, that is directly beneath the component, can be removed. • Ground vias placed near the AC coupling capacitors are essential to provide a direct current return path to the lower GND plane and back. • The minimum impedance mismatch and therefore the optimum structure is achieved when the width of the cut-out beneath the capacitor is 25 mils. • For most applications, a capacitance value of 100nF with an 0402 package for the AC coupling capacitor is adequate. References 1. DC Coupling with 7 Series FPGAs GTX Transceivers, Xilinx. 2. Optimizing Impedance Discontinuity Caused by SM Pads for High-Speed Channel Designs, Altera. 3. AC and DC Coupling: What's the Differ- ence? Siemens. 4. High-Speed Digital Design, Howard John- son. Barry Olney is managing director of In-Circuit Design Pty Ltd (iCD), Australia, a PCB design service bureau that specializes in board- level simulation. The company developed the iCD Design Integrity software incorporating the iCD Stackup, PDN and CPW Planner. The software can be downloaded from www.icd.com.au. To contact Olney, or read past columns, click here. impedance profile of the high-speed differen- tial traces without the plane cut out under the surface mount lands of the AC coupling capaci- tors. The other lines are the impedance profiles with the cut out set to different widths. The simulation results show that the width of the plane cut out plays an important role in minimizing the impedance mismatch. The impedance without the plane cut out is below 75Ω at the capacitor lands. However, this needs to be increased to 100Ω to avoid reflections. The minimum impedance mismatch and there- fore the optimum structure is achieved when the width of the cut out is 25mils. For most applications, a capacitance value of 100nF with a 0402 package, for the AC coupling capacitor, is adequate. This is a basic guideline to follow if you do not have access to a simulation tool. If the lower plane is a power plane or if there is no lower plane, a ground fill can be poured in the region underneath the capacitors and stitched with four GND vias close to each capacitor land. Systems fail for all sorts of reasons, and some of the issues relate to the interaction between reflections across multiple components. Opti- mization is free, and margin–engineering is a non-recurring expense, and as such is free with regards to manufacturing costs. Once done, the margin is always there and costs nothing to implement. Key Points • Discontinuities in the physical geometries, along the transmission path, degrade the signal by loss of amplitude, reduction of rise time, and increased jitter. • A capacitor is typically placed in series with both differential signal traces to remove common mode voltage differences. • AC coupling is useful because the DC component of a signal acts as a voltage offset, and removing it can increase the resolution of the signal and allows different technologies to communicate. • The most important parameter of the AC coupling capacitor is the relative geometry with respect to its environment.

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