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58 PCB007 MAGAZINE I SEPTEMBER 2018 • Mitigation of conductor parasitics (straight metal connects vs. wirebonds) • Effective heat paths leading from single "hot" components through the assembly to the environment Starting from the integrated circuit (IC) foundry, the first packaging step would be eit- her wire-bonding a naked die to a carrier/PCB or re-routing the die-pads (I/Os) into a chip-si- ze- or chip-scale package (CSP) utilizing one side of a die as a redistribution layer (RDL). Any carrier (aka, interposer) as well as CSP may be fitted with connecting metal studs, pil- lars, and bumps, thus providing the option for 2.5D or 3D stacking, not to mention the final soldering of ball grid arrays (BGAs) to a prin- ted circuit. For ease of illustration and clarity any (repe- ated) three-dimensional "component" stacking procedures are intentionally left off in Figure 1. Figure 2 shows the subsequent packaging steps onto carriers prior to component solde- ring to the PCB. Figure 1: Wirebond and redistribution scheme. Figure 2: Stepping forward to subsequent soldering onto printed circuits.

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