Issue link: https://iconnect007.uberflip.com/i/1024460
40 PCB007 MAGAZINE I SEPTEMBER 2018 when tuning very fine, high-density circuits in a stack that may have 12 to 20 layers. Tradi- tional PCB suppliers in the U.S. often still com- municate in mils and have a somewhat expe- rience-based view of build-to-print and accept- able geometries. At the same time, if the appli- cation can get by with 3-mil lines and spaces on polyimide or FR -4, then we are not the right fit. Many of the industry publications and confer- ences highlight state-of-the-art modified semi- additive substrates or wafer level fan-out pack- aging for high-volume applications. We believe our technology has the right mix of fine lines, impedance control, layer count and the exper- tise Benchmark provides for engineering, pro- duction, assembly and integration that is found nowhere else. Beaulieu: Now let's talk about quality. Let me know what qualifications, certifications and registrations you have and why these give you an advantage over other companies. Rathburn: One of the challenges HSIO faced as a company developing promising technol- ogy is that the engineering teams have inter- est and the ability to experiment and explore, but commodity and production teams need a viable, strong supplier base to even consider important components. Historically, custom- ers in the test and development world are less concerned with volume production, certifica- tions, ISO registrations and that is the mar- ket HSIO has served directly in the past. A key advantage of the Benchmark relationship is they are a respected tier EMS company that has the strength, reputa- tion, qualifications and resources to support customers across most markets with all of the commercial require- ments along with the leading-edge technolo- gy and capability that sets them apart from commodity PCB assem- bly and box build. Beaulieu: Jim, I know that much of your work is considered research and development; can you talk about that? Rathburn: Our R&D work is typically driven by a specific customer need that can be applied to multiple customers and multiple markets. We try to avoid science projects that are for the sake of R&D and focus on process develop- ment that can help us make something mean- ingful. We are launching the LCP technolo- gy product at the 25-micron range node and that is a significant improvement with multiple shrinking of conventional technology and sig- nificant opportunity. The focus of our current R&D efforts is what I call Direct Die Attach LCP. The principle is to arrange packaged components without the substrate or interposer and attache the die di- rectly to an LCP module. The evolution is to shrink the current PCB assembly with an LCP PCB, then shrink one step further with direct die attach. The DARPA CHIPS program has a similar philosophy to disintegrate an ASIC de- vice into chiplets that can be assembled onto a substrate and offers the capability to include mixed semiconductor technology beyond monolithic silicon. Our parallel R&D effort is the ability to test these devices at speed as a connected group before they are assembled, while they are being assembled, and after they are assembled. Known good devices are im- portant in this type of assembly, and critical if devices are embedded within an assembly with no possibility of rework. Figure 4: 10-layer LCP substrate PCB with hybrid SMT assembly and flip chip die attach.