Issue link: https://iconnect007.uberflip.com/i/1024460
60 PCB007 MAGAZINE I SEPTEMBER 2018 From Foundry through Assembly Providing a seamless electrical and thermal path from bare die to the final assembly´s en- vironment already starts with the design of an integrated circuit and continues by designing in high-performing bumps, pillars, studs, and vias subsequently on interposers, carriers, sub- strates, and printed circuit boards (Figure 5). At each design stage, extremely different cir- cuit and interconnect dimensions—applicati- on specific—do apply, ranging from µm to mm values (Table 2). These far spanned geomet- ries—visualized in Figure 6—do require diffe- rent electrolytes, different process conditions, and carefully adjusted equipment (tools) for copper plating pillars, studs, bumps, and filled vias/through-holes. Geometry and Chemistry The already cited various and extremely dif- ferent geometries simultaneously have specific requirements on performance, namely: • Coplanarity (current density, feature density, etc.) • Bump shape modulation (chemistry selection, bump opening) And, as always, everyone´s target on cost reduction is impacted by: • Plating speed: from 2-4 µm/min and beyond • Bath life: Photoresist compatibility, additives´ by-products Figure 5: The seamless speedy copper path. Table 2: Typical dimensions and applications along the interconnect seam.