Issue link: https://iconnect007.uberflip.com/i/1024460
SEPTEMBER 2018 I PCB007 MAGAZINE 67 Void generation happens in a two-way direc- tion: Vacancies move towards the copper sub- strate and copper ions diffuse in the opposi- te way—10X faster than tin does, particular- ly in soldering. The relevant thermodynamics go verning the void formation are shown in Figure 14. The same factors cited above foster a perfect 1,1,1 copper cell unit being resistant to Kirken- dall void generation: • Chemistry/conc. (additives per se) • Current density • Temperature • Tool selection • Tool auxiliaries The worst case scenario in Figure 15 has been deliberately chosen for. Naturally, any given impurities (e.g., car- bon-based, by-products, any contaminants) may lead to lattice distortions/defects as well thus preventing a flawless 1,1,1 copper cell formation. The Macro PCB Section: Via Fill and Through-hole plating [7,8] Figure 16 shows a perfectly filled blind microvia (BMV, size 5 x 3 mils) and a simulta- neously copper plated through-hole (diameter = 8 mils). The development and engineering work uses the same routines as for macropillars, as alrea- dy described. For reasons of final qualification, the solid copper post in the BMV was routinely subjected to SEM/XRD to check for the distri- bution of the prevalent Bravais lattices; some basic unit cells are depicted in Figure 17. Again, the preferrable and utmost reliab- le target is the 1,1,1 configuration as shown in Figure 13. Typically on annealing copper at elevated temperatures (e.g., 150 o C, 2 hr.), the proportions of the monitored lattices may sub- stantially change, and the degree of the latter does also impact the overall copper performan- Figure 13: Always preferred—the 1,1,1 copper lattice. Figure 14: Thermodynamics of Kirkendall formation. Figure 15: Kirkendall voids in intermetallic solder layers. (Source: K. Zeng et al., 2005) Figure 16: PCB via fill and TH plating.