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OCTOBER 2018 I DESIGN007 MAGAZINE 77 Results of the eye opening are summarized in Table 2. At the receiving end with one Gbps (i.e., lower-speed grade) transmission, besides 8% attenuation caused by dielectric loss, an additional attenuation of less than 5% is caused by 1.8 inches in total serpentine length. Meanwhile, at the receiving end with 10 Gbps (i.e., higher-speed grade) transmission, besides 15% attenuation caused by dielectric loss, an additional attenuation of less than 5% is caused by the one-inch total serpentine length. With the same total serpentine length, signal transmission at 10 Gbps or higher-speed grade becomes attenuated at a larger magnitude ver- sus one Gbps or lower-speed grade. The plots of Scd21 for microstrip and strip- line are shown in Figure 7. A smaller abso- lute magnitude of Scd21 in dB indicates more easily differential is converted to common mode, which is encountered by channel with larger intra-pair spacing in the serpentine segments. This weakens the immunity of the channel against common mode noise or crosstalk. Summary In PCBs with multi-gigabit signal transmis- sion of 10 Gbps or beyond, the length of the entire serpentine portion shall be kept below 1 inch for differential transmission channel with a total 5 inches in length (i.e., not more than 20% of the total trace length). Meanwhile, the intra-pair gap of serpentine segment shall be less than 2x the non-serpentine segment intra-pair gap to minimize the impedance mis- match and channel loss. This ensures that the attenuation does not exceed 5% of the signal at receiving end without serpentine routing, to allow more head room for channel loss con- tributed by other factors (e.g., dielectric loss, copper surface roughness, etc.). Besides that, due to the weakened immunity of the serpen- tine segments against common mode noise or crosstalk, serpentine routing shall be imple- mented further away (i.e., a distance of at least 5x the transmission channel trace width) from the noise source, (e.g., dielectric loss, copper surface roughness, etc.). DESIGN007 References 1. High-Speed Interface Layout Guidelines, Embedded Pro- cessor Applications, July 2017. 2. Considerations for PCB Layout and Impedance Matching Design in Optical Modules by Daniel Long, February 2011. 3. Keysight ADS guide. Chang Fei Yee is a hardware engineer with Keysight Technologies. His respon- sibilities include embedded system hardware development, and signal and power integrity analysis. Figure 7: Scd21 for microstrip (left) and stripline (right).

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