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56 DESIGN007 MAGAZINE I NOVEMBER 2018 As an example, let's assume a 60-mil FR-4 board is 20 mils wide with 1.0-oz traces on the top layer and at the middle of the board. If the external trace is carrying 2.8 amps, we might find that the external change of temperature is 40°C. From Figure 2 or Equation 1, we can calculate that the internal change of tempera- ture will be 40°C x 0.81 = 32.4°C, which is 7.6°C cooler than the external change of tem- perature. Now, if the trace is 12 mils below the surface instead of the middle of the board (i.e., the trace is at a depth of 12/60 = 0.2), then the difference between the internal tempera- ture and external temperature changes would only be 0.62 times that calculated, or 0.62 x 7.6°C = 4.7°C. The internal change of tem- perature would be 35.3°C (a few degrees hot- ter than at the midpoint), but still cooler than the external trace. There are a few caveats to this analysis. As we point out in our book [3], one of the most important determinants of trace temperature is the thermal conductivity coefficients of the dielectric. There are two such coefficients: one in the in-plane orientation (parallel to the traces), and one in the through-plane orienta- tion (perpendicular to the traces). These coef- ficients relate to the cooling efficiency of the dielectric, and the trace temperature is heavily dependent on them. However, the problem is most material sup- pliers do not specify a thermal conductivity coefficient for their product offerings, and if they do, they typically offer only one value without specifying which coefficient it is. You probably cannot know the coefficients for the materials you are using, and IPC-2152 does not report the applicable coefficients for their measurements. We can be comfortable that the prior analyses apply well to the IPC- 2152 data (since that's where our analyses were derived from). It is less clear how well they will apply to your particular boards and designs. DESIGN007 References 1. IPC-2152, "Standard for Determining Current Carrying Capacity in Printed Board Design," August 2009. 2. National Bureau of Standards (NBS) Report #4283, D.S. Hoynes, "Characterization of Metal-insulator Laminates," May 1, 1956. Commissioned by the U.S. Navy's Bureau of Ships. For more information, see IPC-2152, Appendix A7, p. 85. A copy of the original NBS chart is included in Figure A89, p. 86. 3. Douglas Brooks and Johannes Adam, "PCB Trace and Via Temperatures: The Com- plete Analysis, 2nd Edition" CreateSpace Inde- pendent Publishing Platform, February 2017 (Chapter 4 provides a thorough discussion of trace heating and cooling). 4. Thermal Risk Management (TRM) simu- lation software is available at www.adam- research.com. Douglas Brooks has a BSEE and an MSEE from Stanford and a Ph.D. from the University of Washington. For the last 27 years, he has owned a small engineering service firm, written numerous technical articles on PCB design and signal integrity issues, and published two books on these topics, as well as trace temperatures and currents. Brooks has given seminars several times a year all over the U.S., Moscow, China, Taiwan, Japan, Israel, Australia, and Canada. He primarily focuses on making complex technical issues easily understood by those without advanced degrees. To read past columns or con- tact Brooks, click here. Johannes Adam received a doctorate in physics from Heidelberg University in 1989. He worked on numerical simulations of electronics cooling at software companies like Cisi Ing- enierie S.A., and Flomerics Ltd. and Mentor. In 2009, Adam founded ADAM Research and now works as a technical consultant and software developer for electronics companies. He is the author of a simula- tion program called Thermal Risk Management (TRM) designed for electronics developers and PCB designers who want to solve electro-thermal problems at the board level. He is also a Certified Interconnect Designer (CID) and lives in Leimen, Germany.