Issue link: https://iconnect007.uberflip.com/i/1104607
APRIL 2019 I PCB007 MAGAZINE 25 optimization. There are all sorts of optimization issues to deal with, including motion, sails creat- ing shade, moving with the sun, etc. It's a much smaller, but perhaps even more dynamic envi- ronment than a large-scale solar power station. Katoch: We are actually looking into extending this work to various types of different condi- tions, such as wind variations, humidity, dew point, temperature, etc., where other param- eters also come into play. I am working on de- veloping other applications using these param- eters, so that's in our future. _____________________________ I closed with Goutham and a further expla- nation of his work on fan-out wafer-level pack- aging. Goutham Ezhilarasu: In addition to what I men- tioned earlier, initially, we have a silicon han- dler wafer on which we laminate a thermally de- bondable adhesive tape. We pattern alignment marks on the tape and complementary align- ment marks on the dies to integrate. Then, we can use a standard pick- and-place tool to align and place the die on the tape. We have demonstrated less than one- micron alignment accuracy. When we assemble the die, we pour our molding compound, which is polydimethylsi- loxane (PDMS), a biocompatible, viscoelastic polymer. We use a second silicon handler wa- fer with another adhesive tape but at a higher debonding temperature, which we use to com- pression-mold the PDMS. Once we cure this, we heat the stack to the release temperature of the first adhesive tape so that it comes out. When the handler wafer debonds, we get a very flat surface. Then, we deposit some stress buffer layers. The stress buffer layers are needed as you can- not directly metallize on PDMS due to CTE mis- match between copper and PDMS. We also lith- ographically pattern certain vertical structures called corrugations. Next, we use standard sili- con processing to electroplate copper wires to a thickness of about seven microns, connecting the dies. We repeat this process by putting a di- electric, creating vias and the second metal so that we can get multiple layers of metal. Nolan Johnson: It looks like a Mylar flexible circuit, but you have silicon components built into it. And as you're building up these layers, I can see what would normally be intercon- nects in each of those layers. Ezhilarasu: Yes. Johnson: How many layers can you do? Ezhilarasu: We have shown two, but we are planning to go up to four. We do a bending test down to a one-millimeter bending radius. When we go higher, there's enormous strain. At the one-millimeter bend, when you have so many metal layers, the wires buckle, resulting in some delamination. Johnson: A one-millimeter bend is a pretty ag- gressive test. Ezhilarasu: It's almost like folding. Johnson: This research is part of your work as a doctoral student. What's your intention once you finish your program? Are you pursuing this in the industry or moving on? Ezhilarasu: Most of the work that was done can be pushed out into commercialization, which we intend to do since the process is well-es- tablished. We have already published several papers on this. We are also working with the medical school at UCLA to try to develop a neural implant. That's how we hope to dem- onstrate some real-world applications. Johnson: Give me a sense for the complexity of the circuit you achieve. Are you able to go denser and more complex in this technology than what's currently out there in production? Goutham Ezhilarasu