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54 PCB007 MAGAZINE I JUNE 2019 Article by Brandon Sherrieb INTEGRATED TEST CORPORATION Background A few years ago at Integrated Test Corpora- tion, we found that the reaction plan for void fallout at electrical test was ineffective and not standardized. Like many PCB manufacturing facilities (including a Sanmina shop that I used to work at), the reaction plan consisted of cross section analysis to determine the void type. Then, based on the type of void, we would ei - ther thermal stress and cross section coupons from passing boards or process passing boards through reflow simulation and retest electrical conti- nuity for disposition. In addition to these re- action plans, another that I have experienced at San- mina included one where circuit boards would be processed numerous times through a micro-etch pro- cess and retested for electri- cal continuity if voiding was found within unfilled holes. If the panels withstood that, they should be okay, right? Unfortunately, none of these dis- position methods are robust enough to ensure that vias with marginal connection are caught before shipment. As we all know, a few holes within a coupon is hardly representative of the thousands of holes within a circuit board, and processing production orders through a reflow simulation or micro-etch before assembly will negatively impact the life of that PCB. Therefore, the only way to ensure that mar- ginal products are not being shipped to the customer is to perform an electrical test on those suspect vias at a low enough resistance where minor differences between vias can be ob- served. A method that was evaluated and proven suc- cessful would be four-wire Kelvin testing; if charac- terized properly for your process, it can distinguish differences in copper thick- ness between holes. A fail- ure discovered by this test- ing method is depicted in Figure 1. Kelvin Characterization to Accurately Predict Copper Thickness Figure 1: Example of low copper discovered during Kelvin testing.

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